Cell of flash memory device

Details Cell of flash memory device Cell of flash memory device

1999-10-08

2001-09-18

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S319000, C257S321000, C257S314000, C257S239000

Reexamination Certificate

active

06291855

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly, to a cell of a flash memory device and a method for fabricating the same.
2. Description of the Related Art
In a flash memory device, even when power supply is interrupted, the information stored in a memory cell is not vanished. Thus, the flash memory device is widely adopted to a memory card used for a computer. A unit cell of a typical flash memory device has a gate structure in which a floating gate and a control gate electrode are sequentially stacked.
FIG. 1
is a cross-sectional view of a unit cell of a conventional flash memory device of the prior art.
Referring to
FIG. 1
, a source region
3
a
and a drain region
3
b
isolated from each other with a channel area being therebetween are formed on a semiconductor substrate
1
. A tunnel oxide
5
, a floating gate FG′, a dielectric film
7
and a control gate electrode CG′ are sequentially deposited on the channel area. The semiconductor substrate
1
is a P-type silicon substrate or a P-type well. The source region
3
a
and the drain region
3
b
are areas doped with impurity of a conductivity type different from that of the semiconductor substrate
1
, i.e., N-type impurity layers. Also, the tunnel oxide
5
is formed of a thin thermal oxide having a thickness of 100 Å or less so that hot carriers generated at the channel area may pass through.
The programming operation of the unit cell shown in
FIG. 1
is performed such that a voltage of 5-7 V is applied to the drain region
3
b
and a voltage of 10-12 V is applied to the control gate electrode CG′. Here, 0 V is applied to the source region
3
a
and the semiconductor substrate
1
. In such a manner, if the respective voltages are applied to the control gate electrode CG′, the source region
3
a,
the drain region
3
b
and the semiconductor substrate
1
for programming the unit cell, hot carriers, i.e., hot electrons, are generated at the channel area. The hot carriers pass through the tunnel oxide
5
to then be injected into the floating gate FG′. As a result, the programming operation is performed to increase a threshold voltage of the unit cell shown in FIG.
1
.
Also, the erasing operation of the information stored in the unit cell shown in
FIG. 1
is performed such that the control gate electrode CG′ and the semiconductor substrate
1
are grounded, and a high voltage of 12-15 V is applied to the source region
3
a.
Here, the drain region
3
b
is floated. In such a manner, if the respective voltages are applied to the control gate electrode CG′, the source region
3
a,
the drain region
3
b
and the semiconductor substrate
1
for erasing the unit cell, the electrons stored in the floating gate FG′ pass through the tunnel oxide
5
by a voltage difference between the floating gate FG′ and the source region
3
a
to then move to the source region
3
a.
Accordingly, the electrons in the floating gate FG′ are all removed. As a result, the erasing operation is performed to adjust the voltage of the unit cell to an initial threshold voltage or below.
FIG. 2
is a schematic equivalent circuit diagram for explaining a capacitive coupling ratio of the unit cell shown in FIG.
1
.
Referring to
FIG. 2
, capacitance C
2
caused by the dielectric film
7
exists between the control gate electrode CG′ and the floating gate FG′, and capacitance C
1
caused by the tunnel oxide
5
shown in
FIG. 1
exists between the floating gate FG′ and the semiconductor substrate
1
, i.e., the channel area. Here, if a positive voltage +V
CG
and a positive voltage +V
d
are applied to the control gate electrode CG′ and the drain region
3
b,
respectively, and 0 V is applied to the source region
3
a
and the semiconductor substrate
1
, for programing the unit cell, the voltage V
FG
induced into the floating gate FG′ can be expressed in the following formula (1):
V
FG
≅(
C
2
÷(
C
1
+
C
2
))×
V
CG
  . . . (1)
From the formula (1), it is understood that the voltage induced into the floating gate FG′ is close to the voltage applied to the control gate electrode CG′ as the capacitance C
2
between the control gate electrode CG′ and the floating gate FG′ increases. Thus, if the capacitance C
2
is increased relative to the capacitance C
1
, the programming efficiency can be increased and the programming voltage applied to the control gate electrode CG′ can be reduced.
As a result, in order to increase the programming efficiency of a flash memory cell or reduce the programming voltage, it is necessary to increase the capacitance between a floating gate and a control gate electrode.
SUMMARY OF THE INVENTION
It is an objective of the present invention to provide a flash memory cell which can increase the programming efficiency and can reduce the programming voltage.
It is another objective of the present invention to provide a method for fabricating the flash memory cell.
Accordingly, to achieve the above objective of the present invention, there is provided a floating gate formed as a second conductive film and a control gate electrode on a semiconductor substrate. The floating gate covers a tunnel oxide formed on a predetermined area of the semiconductor substrate and extends to the upper portion of the semiconductor substrate in the vicinity of the tunnel oxide. A first conductive film is interposed between the extending portion of the floating gate covering the tunnel oxide and the semiconductor substrate so that an overlapped portion of the first conductive film and the floating gate exists. An insulation film thicker than the tunnel oxide is interposed between the first conductive film and the semiconductor substrate. The insulation film between the first conductive film and the semiconductor substrate is preferably formed of an isolation film and a gate insulation film, positioned in parallel with each other. Here, the gate insulation film contacts the tunnel oxide and the isolation film contacts the gate insulation film. The insulation film may be formed of only an isolation film. A first interlevel dielectric film is interposed between the floating gate and the first conductive film. The first interlevel dielectric film and the tunnel oxide may be formed simultaneously during the same processing step. A third conductive film is formed on the floating gate. A second interlevel dielectric film is formed between the third conductive film and the floating gate. Also, the third conductive film is electrically connected to the first conductive film in the vicinity of the floating gate. Here, the first conductive film and the third conductive film constitute the control gate electrode. Thus, the control gate electrode extends to the lower portion of edges of the floating gate to increase the overlapped area of the floating gate and the control gate electrode.
The tunnel oxide is preferably formed of a thermal oxide having a thickness of 100 Å or less, and the first and second conductive films are preferably formed of a doped polysilicon film. Also, the third conductive film is preferably formed of a doped polysilicon film or a metal polycide film.
To achieve the second objective, according to the present invention, a first conductive film exposing a predetermined area of a semiconductor substrate is formed on the semiconductor substrate. A tunnel oxide and a first interlevel dielectric film are formed on the surface of the semiconductor substrate exposed by the first conductive film and on the surface of the first conductive film, respectively. An insulation film thicker than the tunnel oxide, e.g., an insulation film formed by a gate insulation film and an isolation film disposed parallel with each other, exists between the first conductive film and the semiconductor substrate. The gate insulation film is formed in the vicinity of the tunne

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