Cell nitride nucleation on insulative layers and reduced...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S303000, C257S306000, C257S534000, C438S243000, C438S386000

Reexamination Certificate

active

06831319

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to fabrication of integrated circuit devices and, more particularly, to methods for forming cell nitride layers and capacitors, and capacitor constructions.
BACKGROUND OF THE INVENTION
Nitride layers are frequently used in the fabrication of semiconductor wafers, for example, in the fabrication of MOSFET gates, memory cells, and capacitors. The nitride layers are utilized as an insulation layer over silicon surfaces to electrically isolate conductive components of a semiconductor circuit from one another. Nitride films are also used as a diffusion barrier to protect regions of a semiconductor wafer during local oxidation of silicon. In a capacitor, a dielectric nitride layer typically separates the upper and lower conductive plates or electrodes.
Various processes are used to produce a nitride layer. One method is by rapid thermal nitridation (RTN), which comprises annealing a silicon layer in an NH
3
or other nitrogen-containing gas that reacts with the silicon to produce silicon nitride. However, the growth of the nitride layer is extremely slow and self-limiting since the NH
3
or other nitrogen-containing gas is not capable of adequately diffusing through the growing silicon nitride layer to react with the underlying silicon. The ultimate thickness of a silicon nitride film produced by nitridation is typically only 3 to 4 nm at high temperatures. Such thickness is usually too low to adequately function as a barrier to prevent further oxidation of the silicon surface during subsequent processing, or as a capacitor dielectric layer between two conductive capacitor plates
Surface properties of the wafer surface play an important role in the initial growth of cell nitride films in thin-film processes, which will impact the properties and structure of the thin film that is deposited. Different nucleation and deposition rates occur for the deposition of nitride on different wafer surfaces. This leads to different or degraded electrical characteristics of semiconductor devices having different wafer surfaces that are fabricated using a nitride deposited layer. In addition, deposition of nitride also includes an incubation time at the start of the deposition where there is no apparent deposition of nitride. The incubation time may extend up to several minutes for some surfaces. Surfaces exhibiting such different rates and incubation times include, for example, borophosphosilicate glass (BPSG), silicon, polysilicon, hemispherical grain (HSG) polysilicon, other doped silicon or polysilicon surfaces, other doped oxides, among others.
An example of a prior art process for forming a DRAM container capacitor is described with reference to
FIGS. 1A-1B
. Referring to
FIG. 1A
, an exemplary semiconductor wafer fragment
10
, shown in a preliminary processing step, comprises a substrate
12
, an insulative layer
14
of borophosphosilicate glass (BPGS) formed over the substrate, an opening
16
patterned and etched into the BPSG layer
14
, and a hemispherical grain (HSG) polysilicon layer
18
formed over the BPSG insulative layer
14
as a bottom electrode or plate of a storage capacitor. As shown in
FIG. 1B
, a nitride dielectric layer
20
is deposited over the HSG silicon layer
18
and the exposed surfaces of the BPSG layer
14
. The dielectric layer
20
will typically comprise silicon nitride (Si
3
N
4
) and/or silicon oxide (SiO
2
), with Si
3
N
4
being generally preferred due to its higher dielectric constant.
Problems have been encountered in connection with the thickness of the cell nitride layer due to the poor nucleation of cell nitride on BPSG and other insulating materials that form the walls of the container capacitor. Due to the poor nucleation, the cell nitride layer on the insulating (BPSG) layer
14
is substantially thinner than on the overlying electrode layer
18
which can comprise a conductive or semiconductive material such as HSG silicon, which is receptive to nitridation. The non-uniformity of the nitride film deposited on various surfaces is caused by the different surface energies of the different substrates. Consequently, in a subsequent cell nitride wet re-oxidation step, the thin nitride layer on the insulating (BPSG) material cannot prevent the electrode (HSG silicon) layer from oxidation, which causes problems with “punch through” of the nitride layer, which diminishes the function of the capacitor. Also as a result of the poor nitride nucleation on the insulating material (e.g., BPSG), a very thin nitride layer is formed at the top corner area
22
of the container where the electrode (e.g., HSG silicon) intersects with the container wall and the insulating (BPSG) material is exposed. This results in high leakage, i.e., “corner leakage,” between the bottom electrode and the top cell plate. Thus, due to the poor nucleation of cell nitride on the insulating (BPSG) material, problems have been encountered with reducing the thickness of cell nitride layers to below 50 angstroms in the manufacture of container capacitors.
A method for forming a uniform nitride layer over different substrate materials is disclosed in U.S. Pat. No. 6,235,571 (Doan), which describes forming a uniform dielectric film layer over a bottom electrode comprising a nitridation receptive material and an insulating material comprising a nitridation resistive material in a storage capacitor fabrication. The method involves depositing a thin layer of non-doped silicon over the bottom electrode and insulating material, and then converting the silicon layer to a silicon nitride compound by thermal nitridation using a nitrogen-containing gas (NH
3
). A silicon nitride layer is then deposited to a desired thickness. A disadvantage of this method is that it requires multiple steps to achieve a uniform nitride layer. The deposition of a very thin silicon nitride layer is very difficult to control.
Therefore, it would be desirable to develop a process of forming a cell nitride layer in a capacitor construction that overcomes such problems.
SUMMARY OF THE INVENTION
The present invention encompasses methods of forming a uniform cell nitride dielectric layer in a semiconductor fabrication, methods of incorporating such dielectric layers into capacitor constructions, and capacitors formed from such methods.
In one aspect, the invention provides methods of forming a uniform nitride dielectric film layer onto a substrate comprising a nitride resistive material such as BPSG or other insulating material, and a nitride receptive material such as HSG silicon or other semiconductive material or a conductive material (e.g., conductive metal). In one embodiment of the method, a surface-modifying agent is implanted into the exposed surfaces of the nitride resistive (BPSG) layer to modify the surface of the layer so as to enhance nitride nucleation in the subsequent formation of a nitride cell layer. Examples of suitable surface-modifying agents include ionizable nitrogen and silicon species. The subsequent deposition of nitride results in a substantially uniform thickness of the cell nitride layer over the nitride resistive (BPSG) portion and the nitride receptive (HSG silicon) portion of the substrate.
In another aspect, the invention encompasses methods of forming a capacitor. In one embodiment, the method comprises forming a first capacitor plate comprising a nitride receptive material such as a semiconductive material, for example, HSG polysilicon, in a container comprising an insulation or nitride resistive material such as BPSG; forming a cell nitride dielectric layer over the first capacitor plate; and forming a second capacitor plate over the cell nitride layer. The cell nitride layer is formed after implanting a surface-modifying agent such as an ionizable nitrogen or silicon species, by low angle implantation onto the exposed surfaces of the insulation or nitride resistive (BPSG) layer adjacent the capacitor container and at the top portion and corners of the container. Preferably, the substrate (e.g., wafer) is rotated during impla

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