Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-10-17
2004-12-07
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S301000, C438S589000
Reexamination Certificate
active
06828203
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the structure of a semiconductor device and a method of manufacturing the same and, more particularly, to an element structure of a Metal Insulator-Semiconductor Field Effect Transistor (to be referred to as a MISFET hereinafter) which is excellent in a high-speed operation and a method of manufacturing the same.
As conventional semiconductor devices using MISFETs, memory devices such as dynamic RAMs or static RAMs formed on silicon substrates, processors using CMOS logic circuits, and the like are mass-produced.
In order to improve the integration density or performance of such a semiconductor device, miniaturization of a MISFET serving as a component is a necessary condition, and development of miniaturization technique and necessity of a short-channel effect and parasitic resistance suppression of the MISFET increase together with transition of generation of a semiconductor device.
As a method of suppressing a short-channel effect, for example, a Lightly Doped Drain structure (to be referred to as an LDD structure hereinafter) shown in
FIG. 1
is known. In a MISFET having the LDD structure, a polysilicon gate
4
is formed on a semiconductor substrate through a gate oxide film
3
, and ion implantation is performed by using the polysilicon gate
4
as a mask, so that shallow impurity diffusion layers
5
are formed on both the sides of the polysilicon gate
4
to be adjacent to a channel region formed at the gate electrode
4
. In addition, gate sidewall spacers
6
are formed on the source/drain sides of the polysilicon gate
4
, and ion implantation is performed by using the gate sidewall spacers
6
and the polysilicon gate
4
as masks, so that deep impurity diffusion layers are formed.
Since the impurity diffusion layers are used as source/drain regions
7
for supplying a drive current of a MISFET, voltage drop is increased by the resistances in the impurity diffusion layers. For this reason, the impurity concentration of this portion must be as high as possible. In order to form a diffusion layer having a high impurity concentration by ion implantation, an amount of implanted impurity per unit area (to be referred to a dose amount hereinafter) must be increased, and an acceleration voltage of ion implantation must be increased.
When the acceleration voltage of impurity ions is increased, the depth of ion implantation increased. For this reason, deep impurity diffusion layers are generally formed in the source/drain regions
7
. When a gate length decreases with miniaturization of the MISFET, the decrease in distance between the source/drain regions adversely affects the threshold voltage of the MISFET and considerably degrades cut-off characteristics of the MISFET.
In order to activate the ion-implanted impurity, a high-temperature heat treatment must be performed. However, at this time, since the impurity is also laterally diffused, the distance between the source/drain regions in which the impurity is deeply implanted more decreases, and it is difficult to suppress the off-leakage current. The changes in characteristics with miniaturization of the MISFET are generally called a short-channel effect.
In order to reduce the short-channel effect in the LDD structure, shallow diffusion layers are formed to be adjacent to both the sides of the polysilicon gate
4
, and the off-leakage current is suppressed such that the distance between the deep diffused layers of the source/drain regions
7
is as large as possible even if the length of the polysilicon gate
4
decreases. Shallow diffusion layers
5
shown in
FIG. 1
are called source/drain extension regions.
In order to reduce the resistances of the source/drain regions
7
and the resistance of the polysilicon gate
4
, as shown in
FIG. 1
, a low-resistance layer constituted by a silicide of high melting point metal
8
is formed on the source/drain regions
7
and the polysilicon gate
4
. Since the silicide of high melting point metal
8
is formed in a self-aligned manner, the structure of the high-speed MISFET is called as a SALICIDE (abbreviation of self-aligned silicide) structure.
In order to improve the performance of the MISFET in a deep submicron region, a gate length must be decreased, and the dimension of depth must also be scaled down in proportion. Therefore, when the short-channel effect is to be reduced in the LDD structure, the shallow extension regions
5
must be formed, and at the same time, the source/drain regions
7
must be made shallow. However, since in general, high impurity concentration layer can not be made shallow, the shallowness of the ion implantation is limited to a predetermined level.
In the SALICIDE structure, as indicated by a broken-line circle in
FIG. 1
, the junction of the extension region
5
becomes close to the end portion of the silicide layer
8
on the drain side, and the formation of the silicide layer
8
on the drain region tend to cause increase a leakage current of a drain junction. The increase in leakage current especially poses a problems at the drain junction to which a large voltage is applied in operation of the MISFET. When an integrated circuit having a high integration level is constituted by CMOS circuits of low power dissipation, it is a necessary condition to remove the leakage current of constituent MISFETs.
In order to avoid the problem of the above LDD structure, an elevated source/drain structure shown in
FIG. 2
is proposed. In this structure, silicon epitaxial layers
51
are grown on source/drain regions, and ions are implanted into source/drain diffusion layers by using gate sidewall spacers
6
and a polysilicon gate
4
as masks. At this time, since the ion implantation is performed through silicon epitaxial layers
51
, the depth of the source/drain regions
7
from the interface of epitaxial layer and silicon substrate
1
is small to suppress a short-channel effect.
However, in the elevated source/drain structure, selective epitaxial growth of silicon at a high temperature of 800° C. or higher is additionally performed, and the number of processing steps increases. At the same time, extra diffusion of impurity implanted in a channel region for threshold voltage control and in the extension regions is advanced. Therefore, this technique cannot always obtain a preferable result as a production technique for a deep submicron region.
Therefore, a means for realizing the structure of a new MISFET having the same advantages as those of an elevated source/drain structure without high-temperature heat treatment processing is strongly demanded.
As shown in
FIG. 2
, in the elevated source/drain structure, when the silicon epitaxial layers
51
are formed on a silicon substrate having (100) surface, (311) facets are easily generated opposite to the polysilicon gate
4
, and parasitic capacitance is formed between the silicide layer
8
and the polysilicon gate
4
. The gate-drain parasitic capacitance disadvantageously degrades the high frequency performance. Here, the facet indicates a small crystal surface having a special crystal orientation.
As another structure for suppressing a short-channel effect, a UMOS structure (to be described below) is known. That is, as shown in
FIG. 3
, a U-shaped deep trench is formed in a semiconductor substrate
1
, source/drain regions
62
and extension regions
61
are formed on the surface of the silicon substrate.
In this UMOS structure, a channel region and a gate insulating film
3
are formed on the inner surface of a deep trench, and a gate electrode
63
is formed to bury the trench. Since source/drain regions
7
have no surfaces which are opposed to each other inside the semiconductor substrate
1
in the structure, the structure is excellent to avoid a short-channel effect. However, since the gate electrode
63
is adjacent to the source/drain regions
62
through the thin gate insulating film
3
, a large gate/drain parasitic capacitance is formed to disadvantageously degrade the high frequency performance of the MISFET.
As described a
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