Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-10-29
2001-07-03
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S238000, C438S239000, C438S241000, C438S258000, C438S396000
Reexamination Certificate
active
06255160
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to integrated circuit semiconductor devices, and more particularly to a method for fabricating dynamic random access memory (DRAM) devices having one or more Gigabits of memory cells. This novel method improves the memory-cell density using auto self-aligning techniques while reducing electrical shorts between the word lines and polysilicon plug contacts. The method also reduces capacitor node leakage currents, and parasitic capacitance. Also reduced are the electrical shorts between the closely spaced polysilicon plugs via keyholes (voids) in the interpolysilicon oxide (IPO) due to poor gap filling with the IPO.
(2) Description of the Prior Art
As integrated circuit density increases, it becomes increasing difficult to manufacture ultra large scale integrated (ULSI) circuits because of process limitations. This problem is particularly acute for making future DRAM devices having more than a Gigabit of memory cells. These process limitations are best understood by referring to the conventional DRAM structure in the prior art
FIGS. 1A and 1B
.
FIG. 1A
shows a portion of a partially completed DRAM cell. Typically a shallow trench isolation (STI)
12
is formed in a silicon substrate
10
surrounding and electrically isolating device (memory cell) areas. A barrier layer
13
, such as silicon nitride (Si
3
N
4
), is deposited and patterned to form openings over the device areas and a gate oxide
14
is grown on the substrate
10
for field effect transistors (FETs). A doped polysilicon layer
16
, a refractory metal silicide layer
18
and an insulating cap layer
20
are deposited and patterned to form word lines (layers
16
,
18
) over the STI
12
while concurrently forming FET gate electrodes over the thin gate oxide
14
. Doped source/drain areas
17
(N) are formed adjacent to the gate electrodes by ion implantation and a conformal insulating layer is deposited and anisotropically plasma etched back to form sidewall spacers
22
on the sidewalls of the FET gate electrodes (patterned layers
16
and
18
). Next an insulating layer
24
is deposited and polished back to form the first interpolysilicon oxide layer (IPO-1) and a photoresist mask and plasma etching are used to etch contact openings that extend over the FET gate electrodes (self-aligned) and down to the source/drain areas. One problem encountered in this conventional self-align process is damage to the source/drain areas
17
when the contact holes are plasma etched. Another problem is the overetching of the cap oxide layer
20
, as depicted at point B in
FIG. 1A
, which can result in shorts to the FET gate electrodes when the contact holes are filled with a doped polysilicon
26
(poly plugs) to make electrical contacts. Also the poly plugs also overlap the gate electrodes resulting in increased parasitic capacitance, resulting in an increased RC time constants and reduced circuit speed. Another problem encountered is poor gap filling between the closely spaced word lines (patterned layers
16
,
18
&
20
) having high aspect ratios, as depicted at point A in FIG.
1
A. When closely spaced contact openings
2
are etched in the insulating layer
24
and into the voids A between the word lines shorts can occur when the contact holes
2
are filled with polysilicon
26
to form the poly plugs. A major shortcoming of the conventional process is the need to align the contact hole extending over the FET gate electrodes, and requires relaxing the alignment rules which makes it difficult to achieve the required density for Gigabit DRAM chips. Still another problem with the conventional process is depicted in
FIG. 1B
for concurrently making borderless contacts
4
to the silicon substrate, that is, contacts that extend over the shallow trench isolation (STI). When contact openings
2
are etched in the insulating layer
24
, it is necessary to use an etch stop layer
13
(Si
3
N
4
) to prevent over etching the STI at the edge and damaging the contact. However, this requires additional process steps.
Numerous methods of making DRAM devices with improved electrical characteristics while increasing memory cell density have been reported. One method is described by Huang in U.S. Pat. No. 5,783,462 in which external contacts for testing stacked capacitor DRAM, but does not address the above problem. Another method for making DRAM devices with increased density and improved sign-to-noise ratio is described by Keeth in U.S. Pat. No. 5,864,181 but also does not address the above concerns. Cherng in U.S. Pat. No. 5,837,577 teaches a method for making DRAM capacitor node contacts self-aligned to. the bit lines but also does not address the above problems.
However, there is still a need in the industry to provide an improved process with novel cell design that is applicable to DRAMs having more than a Gigabit of memory cells. Further while reducing the narrow spacings for Gigabit DRAMS by minimizing the alignment tolerance ground rule, it is also necessary to reduce parasitic capacitance, capacitor node leakage currents, and electrical shorts between closely spaced polysilicon plug contacts to achieve an acceptable circuit performance and an acceptable product yield.
SUMMARY OF THE INVENTION
A principal object of the present invention is to form capacitor-over-bit line (COB) dynamic random access memory (DRAM) devices with increased memory cell density for future DRAM devices with one or more Gigabits of memory cells. The increase in cell density is achieved by using a double auto self-aligned polysilicon contact plugs technique.
A second objective of this invention is to form these high-density memory cells with reduced electrical shorts, reduced parasitic capacitance to word lines and reduced capacitor node leakage current by reducing plasma etch damage at the substrate contacts.
A third objective of this invention is to form the interpolysilicon oxide (IPO) gap filling after the auto-self-aligned polysilicon plugs are formed. This prevents the polysilicon plugs from shorting through keyhole channels (voids) in the IPO while the keyhole cavities between plugs further reduce intralevel capacitance.
Still another objective of this invention is to provide a very cost-effective manufacturing process.
This novel invention is a method for making DRAM devices with one or more Gigabits of memory cell. The method begins by providing a semiconductor substrate, such as a P
−
doped single-crystal silicon having a <100> crystallographic orientation. A relatively thick Field OXide (FOX) is formed that surrounds and electrically isolates device areas on the substrate for the DRAM memory cells. One conventional method of forming the field oxide areas is by a shallow trench isolation (STI) method, as commonly practiced in the industry. Field effect transistors (FETS) are formed next by growing a thin gate oxide on the device areas. A first polycide layer is formed by depositing a heavily N
+
doped polysilicon layer and a refractory metal silicide layer. An insulating layer, such as silicon oxide (SiO
2
), is deposited to form a first cap layer on the polycide layer. The cap layer and first polycide layer are patterned to form the DRAM word lines that also serve as gate electrodes over the device areas. Next N doped source/drain areas are formed adjacent to the gate electrodes and a conformal insulating layer is deposited and anisotropically etched back to form first sidewall spacers on the gate electrodes.
Next a thin conformal diffusion protection oxide layer, such as SiO
2
, is deposited and is patterned to form openings where contacts to the substrate are desired. Then a first conducting layer, preferably composed of an N doped polysilicon is deposited and is chemically-mechanically polished (CMP) back to the first cap oxide layer. A photoresist mask and plasma etching are used to pattern the polished back first conducting layer to form the first contact plugs for bit lines and for capacitor node contacts. The polish-back results in the firs
Ackerman Stephen B.
Kennedy Jennifer M.
Niebling John F.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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