Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
1998-01-15
2001-05-01
Whitehead, Jr., Carl (Department: 2823)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S791000, C438S792000, C438S793000, C438S778000
Reexamination Certificate
active
06225241
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a fabrication method of semiconductor devices, and particularly to that of semiconductor devices having compound semiconductor substrate.
Compound semiconductor materials such as gallium-arsenide (GaAs) or indium-phosphide (InP) have higher electron mobility than silicon (Si), and researches and developments of high-power and high-frequency (microwave or millimeter-wave band) FETs (Field Effect Transistors) making use of the compound semiconductor materials are actively pursued now.
In the high-power compound semiconductor FETs, there is sometimes found a phenomenon where drain current, and consequently, output power decreases during usage. This phenomenon is reported to be owing to active layer erosion of the element brought out by progress of electrochemical oxidation of the semiconductor surface during the usage, and is avoidable by providing a surface passivation film of silicon nitride (SiN), in pp. 115-116, ELECTRONICS LETTERS, vol. 21, No. 3, January 1985.
FIGS. 4A
to
4
D are cross sections schematically illustrating fabrication processes of a conventional high-power GaAs FET, a MESFET (MEtal-Semiconductor FET), by way of example.
Firstly, a mask pattern
8
is printed with photo-resist, for example, on a surface of an n-type GaAs layer
2
on a semi-insulating GaAs substrate
1
for forming a recess
3
by etching a part of n-type GaAs layer
2
of about 300 nm thickness, as illustrated in FIG.
4
A.
Then, whole surface of the n-type GaAs layer
2
is covered with SiN film
20
of about 300 nm thickness deposited from monosilane (SiH
4
) and ammonia (NH
3
) gas, by way of plasma enhanced CVD (Chemical Vapor Deposition), and the SiN film
20
is etched for forming an opening
4
as illustrated in
FIG. 4B
, making use of a photo-resist mask, for example.
Then, a metallic film of WSi, for example, is formed on the whole surface of the substrate
1
by sputtering, which is masked with a photo-resist, for example, and etched for forming a gate electrode
5
, as illustrated in FIG.
4
C.
Then, a source electrode
6
and a drain electrode
7
are formed with liftoff technique as illustrated in
FIG. 4D
in openings configured by etching the SiN film
20
making use of a photo-resist mask, for example.
Thus, a MESFET having a structure as illustrated in
FIG. 4D
is obtained.
HBTs (Heterojunction Bipolar Transistors) made of compound semiconductor materials are also expected as promising devices for high-power and high-frequency amplifiers, and research and development thereof are active as well. Among them, emitter-top type AlGaAs/GaAs HBTs having a mesa structure are most developed now.
In these mesa type HBTs, when device size thereof is made fine for improving high-frequency performance, a problem called the emitter-size effect becomes important, wherein recombination current flowing out at the edge of emitter mesa becomes large compared to the base current, resulting in current gain decline.
As a method for reducing the emitter-size effect, there is disclosed a guard-ring technique in a Japanese patent application laid open as a Provisional Publication No. 286126/'92, for example, wherein a ledge structure, that is, an extrinsic base protection layer of about 50 nm thickness is provided around the emitter mesa.
However, there are problems in these prior arts.
In the MESFET of
FIGS. 4A
to
4
D, the SiN surface passivation film
20
is deposited by plasma enhanced CVD, and so, the surface of the n-type GaAs layer
2
is damaged by the plasma and binding of Ga and As is weakened there. Hence, a low resistance part
10
is formed on the surface traversing the gate
5
and the drain
7
as illustrated in
FIG. 5
, because of As estranged during the usage. The low resistance part
10
degrades breakdown voltage because of increase of the gate leak current. This is a problem.
Further, electron traps are also derived on the surface of the n-type GaAs layer
2
damaged by the plasma, which are charged and discharged with a longer time constant than that of the designed element (phenomenon called the gate-lag) when the element operates at a high frequency, decreasing effective drain current.
Still further, the SiN film
20
deposited by the plasma enhanced CVD includes hydrogen of 20 to 30 atom %. According to these free hydrogen atoms, electron traps are derived also in the SiN film
20
, which degrade too the breakdown voltage by charging and discharging themselves when electric field is impressed.
Besides these problems, the SiN film
20
deposited by the plasma enhanced CVD has compressive internal stress of about 3×10
9
dyn/cm
2
. Therefore, piezoelectricity is generated in the n-type GaAs layer
2
according to interfacial tension between the n-type GaAs layer
2
and the SiN film
20
, which becomes a cause of the threshold voltage dispersion of the narrow gate FET. This is another problem.
As for the above described HBT having the extrinsic base protection layer, it must have such an epitaxial layer structure that a narrow band-gap material of InGaAs layer is inserted between the emitter layer and the base layer for precisely configuring the extrinsic base protection layer. However, there is a problem that electrons are charged in the InGaAs layer, generating a potential barrier which decreases emitter current, besides the problem of the complicated epitaxial layer structure needing intricate and high-cost processes for developing its lamination.
SUMMARY OF THE INVENTION
Therefore, a primary object of the present invention is to provide a fabrication method of compound semiconductor devices which can improve the problems above described of the prior MESFET, such as the breakdown voltage degradation owing to increase of the gate leak current or the electron traps in the surface passivation film, the drain current decrease because of the gate-lag, or the threshold voltage dispersion caused by the interfacial tension.
Another object of the invention is to provide a fabrication method of compound semiconductor devices which can easily restrain the emitter-size effect of the prior mesa type HBT, without revising or complicating its epitaxial layer structure.
In order to achieve the object, a fabrication method according to the invention of a semiconductor device, having a high-resistance film covering a part of a surface other than electrodes of the semiconductor device, comprises a step of depositing the high-resistance film by way of catalytic CVD.
The fabrication method preferably further comprises a step of surface cleaning performed before the step of depositing for cleaning the surface of the semiconductor device by a gas including active hydrogen flowing on the surface.
As for the high-resistance film, a material including no oxygen such as SiN is applied.
In the catalytic CVD, material gases are cracked and made active by contacting catalyzer surface of high temperature. The activated material gases react in the same way with those in the thermal CVD. Further, in the catalytic CVD, the temperature of the catalyzer can be controlled independent of the substrate temperature. Therefore, a deposition film having the same quality can be obtained with lower substrate temperature in the catalytic CVD than in the thermal CVD.
REFERENCES:
patent: 5043299 (1991-08-01), Chang et al.
patent: 5731235 (1998-03-01), Srinivasan et al.
patent: 4-286126 (1992-10-01), None
by M.R. Matthews et al., “Comparative Reliability Study of GaAa Power MESFETs: Mechanisms for Surface-Induced Degradiation and a Reliable Solution”,Electronics Letters,vol. 21, No. 3, Jan. 1985, pp. 115-116.
Matsumura, “Low Temperature Deposition of Silicon Nitride by the Catalytic Chemical Vapor Deposition Method, ” Jap. J. Appl. Phys., vol. 28, No. 10 Oct., 1989, pp. 2157-2161.
Berezny Neal
Jr. Carl Whitehead
NEC Corporation
Young & Thompson
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