Cascaded multiple internal phase-locked loops for synchronizatio

Details Cascaded multiple internal phase-locked loops for synchronizatio Cascaded multiple internal phase-locked loops for synchronizatio

1998-07-30

2000-08-29

Heckler, Thomas M.

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

39550013, G06F 112

Patent

active

061123080

ABSTRACT:
Methods and apparatus for easing design constraints with respect to placement of computer system components and subsystems requiring relative synchronicity is described. In one embodiment the apparatus includes a first and a second integrated circuit wherein each integrated circuit includes a first phase-locked loop (PLL) formed on an integrated circuit die. A reference clock signal pin is coupled to the first PLL by a path of electrical length L1 for propagating a reference clock signal to the first PLL. A first PLL driver is coupled to the first PLL. A first PLL feedback pin is coupled to the first PLL by a path of electrical length L2, wherein L1.apprxeq.L2. The first and second integrated circuits are cascade-coupled by coupling the first PLL driver of the first integrated circuit to the reference clock signal pin of the second integrated circuit using a propagation path of electrical length L3. In one embodiment a feedback path of electrical length L4 couples the first PLL driver and feedback pin of the first integrated circuit such that L3.apprxeq.L4. In one embodiment L1, L2, L3, and L4 have corresponding physical lengths D1, D2, D3, and D4, wherein D1.apprxeq.D2 and D3.apprxeq.D4. The cascaded integrated circuits enable providing synchronicity between components of a same tier as well as between multiple tiers of a hierarchical computer system architecture.

REFERENCES:
patent: 3567914 (1971-03-01), Neese et al.
patent: 5544088 (1996-08-01), Aubertine et al.

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