Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Plasma
Reexamination Certificate
2001-03-15
2002-09-17
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Plasma
C438S714000
Reexamination Certificate
active
06451673
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to improved methods for performing plasma etching for forming a pattern of recessed features in a substrate, e.g., via openings and/or trenches in a dielectric layer overlying a semiconductor substrate comprising at least one active device or region, utilizing an overlying mask including a pattern of openings corresponding to the pattern of features to be formed in the substrate. The present invention enjoys particular utility in semiconductor manufacture wherein ultra-thin metallization pattern masks are employed during reactive plasma etching for forming openings or recesses in a dielectric layer as part of multi-level metallization processing for formation of high integration density, semiconductor integrated circuit (“IC”) devices having submicron-dimensioned design features.
BACKGROUND OF THE INVENTION
The escalating requirements for high integration density and performance associated with ultra large-scale (“ULSI”) integration semiconductor device wiring and interconnection are difficult to satisfy in terms of providing submicron-dimensioned (e.g., 0.18 &mgr;m and below, such as 0.15 &mgr;m and below), low resistance-capacitance (“RC”) time constant metallization patterns, particularly when the submicron-dimensioned features such as vias, contact areas, grooves, trenches, etc., have high aspect (i.e., depth-to-width) ratios due to micro-miniaturization, and accordingly, responsive changes in interconnection technology are required.
Conventional semiconductor IC devices typically comprise a semiconductor substrate, such as a monocrystalline silicon (Si) wafer including a plurality of active device regions formed thereon or therein, and a plurality of pairs of overlying, sequentially formed inter-layer dielectrics (“ILD”s) and patterned metal layers. An integrated circuit is formed therefrom containing a plurality of electrically conductive patterns comprising conductive lines separated by interwiring spaces, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns of different layers, i.e., upper and lower vertically spaced-apart layers, are electrically connected by a conductive plug filling a via opening, while a conductive plug filling a contact opening establishes an electrical contact with an active device region on or in the semiconductor substrate, such as a source or drain region of a transistor. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor IC devices comprising five (5) or more such levels of vertically interconnected metallization are becoming more prevalent as device geometries decrease into the deep submicron range.
A conductive plug filling a via opening is typically formed by a process sequence comprising: (1) depositing an inter-layer dielectric (“ILD”) on a patterned, electrically conductive layer, e.g., a metal layer comprising at least one metal feature; (2) forming a desired opening in the ILD, as by conventional photolithographic masking and etching techniques, and filling the opening with an electrically conductive material, e.g., tungsten (W); and (3) removing excess conductive material deposited on the surface of the ILD during filling of the opening, as by chemical-mechanical polishing/planarization (“CMP”).
One such method for fabricating electrically conductive vias is termed “damascene” type processing and basically involves the formation of an opening in the ILD which is filled with a metal plug. “Dual-damascene” processing techniques involve formation of an opening in an ILD comprising a lower, contact or via opening section communicating with an upper, trench opening section, followed by filling of both the lower and upper sections of the opening with an electrically conductive material, typically a metal or metallic material, to simultaneously form a conductive (via) plug in electrical contact with a conductive line.
A drawback associated with the use of damascene technology for forming submicron-dimensioned, in-laid metallization patterns and features arises from the loss of the “critical dimension” (CD) of the mask utilized in the step for forming the recesses in the dielectric layer according to conventional reactive plasma etching process for obtaining the requisite anisotropic etching of the dielectric layer, which loss of CD is attributed to sputter etching of the mask material due to bombardment thereof by ions of the carrier gas/diluent for the reactive plasma etching gas which are generated in the plasma. Loss of CD can pose a significant problem in forming recesses and metallization features according to particular design rules. In addition, the problems associated with loss of CD arising from deleterious sputter etching of the masking material is exacerbated by the requirement for use of ultra-thin layers of masking layers, e.g., from about 300 to about 1,500 Å thick, when fabricating ULSI devices having feature sizes below about 0.18 &mgr;m and with high aspect ratios.
Adverting to FIGS.
1
(A)-
1
(C), shown therein in simplified, cross-sectional schematic form, are views successively illustrating initial, intermediate, and final stages of a conventional reactive plasma etching process for forming submicron-dimensioned recesses in a dielectric layer, utilizing a patterned mask having an initial CD. Referring more particularly to FIG.
1
(A), a workpiece
1
is provided in an initial state, comprising a substrate
2
, typically of a semiconductor such as a wafer of monocrystalline silicon (Si) or gallium arsenide (GaAs) including at least one active device region or layer formed therein or thereon; a dielectric layer
3
, such as an ILD layer, formed on the upper surface of substrate
2
and comprised of one or more inorganic- and/or organic-based dielectric materials, e.g., a low dielectric constant (“low k”) material; and a thin, patterned masking layer
4
formed on the upper surface of the dielectric layer
3
and including at least one opening
5
formed therein, as by conventional photolithographic masking and etching techniques, the opening
5
having a critical dimension CD, e.g., for defining the width or diameter of a trench or groove to be formed in the underlying dielectric layer
3
. When utilized in the formation of recesses with design features in the submicron range, the thin mask layer
4
preferably is ultra-thin (e.g., from about 300 about 1,500 Å thick and may be formed of an organic-based photoresist material (e.g., an acetal-type UV-sensitive resin) or an inorganic-based hard mask material (e.g., a silicon nitride).
Referring now to FIG.
1
(B), the workpiece
1
including the patterned masking layer
4
is installed within the interior space of a plasma etching chamber and subjected to conventional, anisotropic, reactive plasma etching utilizing a halogen-containing reactive plasma, e.g., a fluorine-containing plasma, for forming a recess
6
in the surface of the dielectric layer
3
, the reactive plasma being generated by supplying a gaseous mixture of at least one halogen containing gas (e.g., CCl
4
, CF
4
, C
4
F
8
, CCl
2
F
2
, etc.) as a reactive plasma etching gas, optionally admixed with at least one of oxygen (O
2
) gas, nitrogen (N
2
) gas, and hydrogen (H
2
) gas), and argon (Ar) as an inert carrier gas/diluent for the reactive plasma etching gas, to the plasma etching chamber while maintaining the interior space thereof at a reduced pressure and applying radio frequency (“RF”) of microwave (“&mgr;wave”) electrical power thereto (e.g., at a power of about 1500 W) to generate a reactive plasma therein. FIG.
1
(B) illustrates the etch profiles of workpiece
1
approximately half-way through the etching process. As shown therein, portions
4
′ (represented by dashed lines in the figure) of the thin masking layer
4
bordering the mask opening
5
have been lost (i.e., consumed) due to sputtering therefrom which is incidental to the reactive e
Gabriel Calvin T.
Okada Lynne A.
Nelms David
Nhu David
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