Capacitorless DRAM with cylindrical auxiliary gate and...

Details Capacitorless DRAM with cylindrical auxiliary gate and... Capacitorless DRAM with cylindrical auxiliary gate and...

2007-01-04

2009-12-15

Sarkar, Asok K (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE27084, C257SE27085, C257SE21613, C257SE21646, C438S142000, C438S144000

Reexamination Certificate

active

07633117

ABSTRACT:
Provided are a capacitorless DRAM (dynamic random access memory) and a fabrication method thereof. In a capacitorless DRAM, a pair of cylindrical auxiliary gates is formed within a bulk substrate. Thus, a volume of a channel body formed at a region where the cylindrical auxiliary gates contact with each other can be increased, while an area of a junction region where the channel body contact source and drain regions can be reduced. As a result, capacitance of the channel body can be increased, and a generation of leakage current through the second junction region can be reduced. The application of a back bias to the cylindrical auxiliary gates can improve a charge storage capability of the channel body.

REFERENCES:
patent: 5698869 (1997-12-01), Yoshimi et al.
patent: 6861689 (2005-03-01), Burnett
patent: 2005/0026354 (2005-02-01), Bhattacharyya
patent: 2006/0278926 (2006-12-01), Mathew et al.
patent: 8-213622 (1996-08-01), None
patent: 2003-31696 (2003-01-01), None

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