Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-05-23
2003-01-28
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S307000
Reexamination Certificate
active
06512259
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a capacitor in an integrated circuit having a noble-metal-containing first electrode, in which a high-∈ dielectric material or a ferroelectric material is used as the capacitor dielectric.
Capacitors are required in a large number of semiconductor integrated circuits, for example in DRAM circuits or A/D converters. A primary aim in this context is to increase the integration density, i.e. it is necessary to achieve as high a capacitance as possible, or a capacitance which is sufficient for the requirements, with a minimum amount of space. The problem presents itself in particular in DRAM circuits, in which each memory cell has a storage capacitor and a selection transistor, while the area available for a memory cell is being constantly reduced. At the same time, in order for the charge to be reliably stored and for it to be possible to distinguish between the information to be read, it is necessary to maintain a certain minimum capacitance of the storage capacitor. This minimum capacitance is currently regarded as being approximately 25 fF.
To reduce the space required for a capacitor, it is possible to use a paraelectric material with a high permittivity (high-∈ dielectric material) as the capacitor dielectric. In memory configurations such capacitors are preferably employed as so-called stacked capacitors (the capacitor of the cell is arranged above the associated selection transistor). Memory cells which use paraelectric material as the capacitor dielectric lose their charge when the supply voltage is selected, and thus lose their stored information. Furthermore, owing to the residual leakage current, these cells have to be constantly rewritten (refresh time). By contrast, the use of a ferroelectric material as the capacitor dielectric, owing to the different polarization directions of the ferroelectric material, makes it possible to construct a nonvolatile memory (FRAM), which does not lose its information when the supply voltage is selected and also does not have to be constantly rewritten. The residual leakage current of the cell does not affect the stored signal.
Various high-∈ dielectric materials and ferroelectric materials are known from the literature, for example barium strontium titanate (BST), strontium titanate (ST) or lead zirconium titanate (PZT), as well as ferroelectric and paraelectric polymers, and other materials.
Although these materials do have the desired electrical properties, their significance in practice still remains limited. A principal reason for this is that the materials cannot be readily employed in semiconductor configurations. The materials are produced by means of a sputter-on or deposition process which requires high temperatures in an oxygen-containing atmosphere. Consequently, the conductive materials (e.g. polysilicon, aluminum, or tungsten) used in the semiconductor industry as electrode material are unsuitable, since they are oxidized under such conditions. Therefore, at least the first electrode is usually made from a noble-metal-containing material, such as platinum or ruthenium. However, these new electrode materials are relatively unknown substances in the semiconductor industry and are relatively difficult to apply. A particularly serious problem is that they can only be structured satisfactorily with a thin layer thickness. Furthermore, they are permeable to oxygen, with the result that, during the production of the capacitor dielectric, deep structures become oxidized and satisfactory contact between the first electrode and selection transistor is not guaranteed. Therefore, a barrier which suppresses oxygen diffusion is required beneath the capacitor dielectric.
German published patent application DE 196 40 448 and published International Application WO 98/14992 describe a memory cell of this type, in which the barrier between the first electrode and the connection structure for the selection transistor is formed over the entire surface by nitriding. German published patent application DE 196 40 244 describes a capacitor with a high-∈ dielectric or ferroelectric capacitor dielectric, in which the first electrode comprises an electrode core and a comparatively thin noble-metal-containing layer, and in which the electrode core comprises the material of the connection structure or of the oxidation barrier. This has the advantage that only a thin noble-metal-containing layer has to be structured.
A common feature of all these capacitors having a high-∈ dielectric or ferroelectric capacitor dielectric is that the first electrode is provided in essentially planar configuration.
In U.S. Pat. No. 5,581,436, a thin layer of platinum is applied to the surface of an electrode core, as the first electrode of a capacitor of the type in question. If appropriate, the high-∈ dielectric may be produced as an exposed structure prior to the formation of the first and second electrodes, i.e. the electrodes are then formed on the side walls of the dielectric.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a capacitor with a high-∈ dielectric or ferroelectric capacitor dielectric, which overcomes the above-mentioned disadvantages of the heretofore-known devices of this general type and which leads to a further reduction in the space requirement. With the foregoing and other objects in view there is provided, in accordance with the invention, a process for producing a capacitor in a semiconductor configuration on a substrate, which comprises:
forming a sequence of layers on a substrate, the sequence alternately comprising a layer of a first material and a layer of a second material, wherein the first material is selectively etchable with respect to the second material;
etching the sequence of layers to form a layer structure with flanks;
forming a first auxiliary structure of a first auxiliary material covering at least one flank of the layer structure, wherein the first auxiliary structure is selectively etchable with respect to the second material;
forming a second auxiliary structure covering at least one other flank of the layer structure and mechanically connecting the layers of the second material;
covering a substrate surface surrounding the layer structure with a filler layer up to a top edge of the layer structure;
removing the layers of the first material and the first auxiliary structure selectively with respect to the layers of the second material and with respect to the second auxiliary structure;
filling a cavity formed in the removing step with a noble-metal-containing electrode material and forming a first electrode with lamellae in the cavity formed by the layers made from the first material and with a support structure connecting the lamellae in the cavity formed by the first auxiliary structure;
removing the layers of the second material and the second auxiliary structure selectively with respect to the electrode material;
conformally applying a capacitor dielectric of a material selected from the group consisting of high-∈ dielectric and ferroelectric material to an exposed surface of the first electrode; and
forming a second electrode on the capacitor dielectric.
In accordance with an added feature of the invention, the first material is undoped, n-doped, and p
−
-doped polysilicon, and the second material is p
+
-doped polysilicon.
In accordance with an additional feature of the invention, the first auxiliary structure is formed on two flanks of the layer structure which lie opposite one another in a first direction.
In accordance with another feature of the invention, the second auxiliary structure is formed on two flanks of the layer structure which lie opposite one another in a second direction.
In accordance with a further feature of the invention, the first auxiliary structure and/or the second auxiliary structure are formed by selective silicon deposition.
In accordance with again an added feature of the invention, the second auxiliary structure is formed by incl
Lange Gerrit
Schlösser Till
Greenberg Laurence A.
Ho Tu-Tu
Infineon - Technologies AG
Locher Ralph E.
Nelms David
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