Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-08-26
2002-03-19
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S239000, C438S240000, C438S250000, C438S251000, C438S393000, C438S394000, C438S396000, C438S003000, C438S660000, C438S663000
Reexamination Certificate
active
06358794
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a capacitor in a semiconductor device and method of fabricating the same which prevents the resistance between its lower electrode and plug from increasing.
2. Discussion of Related Art
A variety of research has been performed for increasing the capacitance density of a semiconductor device to allow the capacitor to have a specific amount of capacitance even if the cell area becomes smaller as the device is more highly integrated. To obtain a large amount of capacitance, the capacitor's lower electrode is formed in three-dimensional structure, for example, stacked or trench structure, enlarging the surface area of the dielectric of the capacitor. However, the stacked or trench structured capacitor is fabricated through a complicated process. Accordingly, there are limitations on increasing the surface area of the dielectric. To solve this problem, there has been developed a method of enlarging the capacitance in which the dielectric is made of a material of a high dielectric constant, such as Ta
2
O
5
, PZT(Pb(ZrTi)O
3
), PLZT((PbLa)(ZrTi)O
3
), PNZT(Pb(NbZrTi)O
3
), PMN(Pb(MgNb)O
3
), BST((BaSr)TiO
3
).
FIG. 1
is a cross-sectional view of a capacitor according to a related art. Referring to
FIG. 1
, N-type impurity region
13
is formed in semiconductor substrate
11
, which serves as source and drain regions of a transistor including a gate (not shown in the drawing). Insulating interlayer
15
is formed on semiconductor substrate
11
to cover the transistor. Contact hole
17
exposing impurity region
13
is patterned in insulating interlayer
15
. Impurity doped polysilicon is filled in contact hole
17
to form a plug
19
which is electrically connected to impurity region
13
. Specifically, plug
19
is formed in such a manner that the doped polysilicon is deposited through CVD (chemical vapor deposition) and then etched back using RIE (reactive ion etching), to expose interlevel insulating layer
15
.
Barrier layer
21
and lower electrode
23
are sequentially deposited on insulating interlayer
15
including plug
19
. Barrier layer
21
which comes into contact with plug
19
is formed of TiN or TaN. Lower electrode
23
is formed in a manner that an oxidation-resist metal like Pt, Mo or Au, or metal whose oxide has conductivity such as Ir or Ru is deposited on barrier layer
21
. Barrier layer
21
prevents the metal forming lower electrode
23
from reacting with silicon composing plug
19
and forming silicide. This is because the silicide is easily oxidized to be changed into an insulating material.
Dielectric layer
25
is formed on insulating interlayer
15
to cover lower electrode
23
. Dielectric layer
25
is formed of a material having a high dielectric constant, for example, Ta
2
O
5
, PZT(Pb(ZrTi)O
3
), PLZT((PbLa)(ZrTi)O
3
), PNZT(Pb(NbZrTi)O
3
), PMN(Pb(MgNb)O
3
) or BST((BaSr)TiO
3
). Upper electrode
27
is formed of the same metal as lower electrode
23
on dielectric layer
25
. When lower and upper electrodes
23
and
27
are formed of an oxidation-resist metal, they are prevented from being oxidized even if they come into contact with dielectric layer
25
. When the electrodes are formed of the metal whose oxide has conductivity, their resistances do not increase because they have conductivity even when they are oxidized.
FIGS. 2A
to
2
D are cross-sectional views showing a method of fabricating the conventional capacitor. Referring
FIG. 2A
, insulating interlayer
15
is formed on P-typed semiconductor substrate
11
including N-type impurity region
13
serves as source and drain regions of a transistor having a gate (not shown). The insulating interlayer
15
P-typed semiconductor substrate
11
copy is then patterned through photolithography, forming contact hole
17
exposing impurity region
13
. Referring to
FIG. 2B
, impurity doped polysilicon is deposited by CVD on insulating interlayer
15
, to fill up contact hole
17
. In this case, the polysilicon comes into contact with the exposed impurity region
13
through contact hole
17
. Thereafter, the polysilicon is etched back using RIE to expose insulating interlayer
15
. By doing so, the polysilicon is left only in contact hole
17
, forming plug
19
.
Referring to
FIG. 2C
, TiN or TaN is deposited on insulating interlayer
15
to come into contact with plug
19
, and forming barrier layer
21
. Oxidation-resistant metal like Pt, Mo or Au, or metal whose oxide has electric conductivity such as Ir or Ru is deposited on barrier layer
21
, to form lower electrode
23
. Here, barrier layer
21
prevents lower electrode
21
from being reacted with plug
19
, thereby eliminating the formation of the silicide silicide between barrier layer
21
and plug
19
. Lower electrode
23
and barrier layer
21
are patterned through photolithography, to be left on a predetermined area of insulating interlayer
15
including contact hole
17
. In this case, lower electrode
23
and barrier layer
21
are patterned to have barrier layer
21
come into contact with plug
19
.
Referring to
FIG. 2D
, a material having a high dielectric constant, for example, Ta
2
O
5
, PZT(Pb(ZrTi)O
3
), PLZT((PbLa)(ZrTi)O
3
), PNZT(Pb(NbZrTi)O
3
), PMN(Pb(MgNb)O
3
) or BST((Ba Sr)TiO
3
) is deposited on insulating interlayer
15
to cover lower electrode
23
, thereby forming dielectric layer
25
. Here, when lower electrode
23
is formed with oxidation-resistant metal, it is prevented from being oxidized even if it comes into contact with dielectric layer
25
having an oxygen component. When lower electrode
23
is formed with a material whose oxide has electric conductivity, such as Ir or Ru, its resistance does not increase because it has electric conductivity even when oxidized.
Oxidation-resistant metal like Pt, Mo or Au, or metal whose oxide has conductivity, for example, Ir or Ru, is deposited on dielectric layer
25
, to form upper electrode
27
. That is, upper electrode
27
is formed of the same material as lower electrode
23
. When upper electrode
27
is formed with an oxidation-resistant metal, it is prevented from being oxidized even if it comes into contact with dielectric layer
25
. When upper electrode
27
is formed with a material whose oxide has electric conductivity, its resistance does not increase because it has conductivity even when oxidized. Upper electrode
27
and dielectric layer
25
are patterned, being left only on a portion corresponding to lower electrode
23
. Only the portion of dielectric layer
25
, which is placed between lower and upper electrodes
23
and
27
, is used as dielectric storing charges.
As described above, the capacitance of the capacitor according to the related art increases because the dielectric layer is made of a material having a high dielectric constant. However, oxygen for forming the material with a high dielectric constant is diffused through the sides of the barrier, when the dielectric layer is formed, to oxidize the barrier layer. This increases the contact resistance between the plug and lower electrode.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a capacitor of a semiconductor device and method of fabricating the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a capacitor which prevents the contact resistance between the plug and lower electrode from increasing due to oxidation of the barrier layer.
Another object of the present invention is to provide a method of fabricating a capacitor, which prevents the barrier layer from being oxidized, to keep the contact resistance between the plug and lower electrode from increasing.
To accomplish the objects of the present invention, there is provided a capacitor of a semiconductor device, which includes a semiconductor substrate, an insulating interlayer formed on the semiconductor substrate, the insulating interlayer having a contact hole which exposes a
Hyundai MicroElectronics Co., Ltd.
Kennedy Jennifer M.
Niebling John F.
LandOfFree
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