Capacitor of semiconductor device

Details Capacitor of semiconductor device Capacitor of semiconductor device

2000-04-11

2002-04-30

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S295000, C257S296000, C257S297000, C257S303000, C257S306000, C257S307000, C257S308000, C257S309000, C257S310000, C257S757000, C257S767000, C438S244000, C438S253000, C438S393000, C438S394000, C438S395000, C438S396000, C438S250000, C361S015000

Reexamination Certificate

active

06380579

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a capacitor of a semiconductor device and a method for manufacturing the same.
2. Description of the Related Art
Semiconductor devices include unit cells. A unit cell of a DRAM device consists of a cell capacitor and an access transistor. The cell capacitor directly affects the characteristics of the DRAM device. As the cell capacitance increases, a soft error rate (SER) is reduced and a low voltage operation characteristic is improved. However, as the circuit integration density of the DRAM device increases, the area occupied by the unit cell is reduced. Accordingly, in order to improve the reliability and the electrical characteristics of a highly integrated DRAM device, a cell capacitor having a capacitance larger than a certain value must be fabricated within the restricted area size of the DRAM device.
Recently, in order to increase the cell capacitance, a material layer having a high dielectric constant, such as a tantalum oxide (Ta
2
O
5
) layer, an aluminum oxide (Al
2
O
3
) layer, a barium, strontium and titanium (BST) layer ((Ba,Sr)TiO
3
), a lead, zirconium, and titanium (PZT) layer ((Pb,Zr)TiO
3
), or a lead, lanthanum, zirconium, and titanium (PLZT) layer ((Pb,La,Zr)TiO
3
), was adopted as a dielectric layer interposed between a storage electrode and a plate electrode in order to increase the cell capacitance. However, a high dielectric layer such as either the Ta
2
O
5
layer, the BST layer, the PZT layer, or the PLZT layer must be deposited by a sputtering process, an atomic layer deposition (ALD) process, or a chemical vapor deposition (CVD) process and thermally treated at a temperature of about 550° C. to 750° C. When the storage electrode is formed of a polysilicon layer, the storage electrode is oxidized. Accordingly, the thickness of the dielectric layer increases or an intersurface characteristic between the dielectric layer and the storage electrode deteriorates, thus deteriorating the leakage current characteristic of the dielectric layer. Therefore, the storage electrode of a capacitor employing the high dielectric layer having the high dielectric constant must be formed from an oxidation-resistant metal layer or a metal oxide layer having excellent conductivity. A platinum (Pt) layer is widely used as the oxidation-resistant metal layer. A ruthenium oxide (RuO
2
) layer is widely used as the metal oxide layer having excellent conductivity. The storage electrode is preferably manufactured to have a three-dimensional shape, for example, the storage electrode may be cylindrical in order to increase the capacitance of the capacitor formed within the size restricted cell area.
FIGS. 1 through 3
are sectional views describing a method for manufacturing a conventional cylindrical capacitor. As shown in
FIG. 1
, an interlayer dielectric layer is formed on a semiconductor substrate
1
. An interlayer dielectric layer pattern
3
, including a storage node contact hole which exposes a predetermined region of the semiconductor substrate
1
, is formed by patterning the interlayer dielectric layer. A contact plug
5
, which contacts the semiconductor substrate
1
, is formed from a conductive material such as tungsten (W) and is placed in the storage node contact hole.
Referring to
FIG. 2
, a sacrificial insulating layer
7
is formed on the entire surface of the semiconductor substrate. The sacrificial insulating layer pattern
7
includes a hole exposing the contact plug
5
. A conductive layer
9
is formed over the entire surface of the semiconductor substrate over the sacrificial insulating layer pattern
7
. The conductive layer
9
is made from an oxidation-resistant metal layer, such as a platinum (Pt) layer, or a conductive metal oxide layer, such as a ruthenium oxide (RuO
2
) layer.
Currently, the oxidation-resistant metal layer and the conductive metal oxide layer are difficult to form using a chemical vapor deposition (CVD) method. Accordingly, the conductive layer
9
is generally formed by a well-known sputtering method. However, the sputtering process show problems associated with poor step coverage. As a result, the thickness T
2
of the conductive layer
9
as formed on the side wall of the sacrificial insulating layer pattern
7
, is less than the thickness of TI, where the conductive layer
9
is formed on an upper surface of the sacrificial insulating layer pattern
7
. Efforts to increase the thickness of T
2
using the sputtering method renders the thickness T
1
to become very thick. Since the cost of the material layer used for the conductive layer
9
is high, the manufacturing cost of the semiconductor device increases with the use of thicker material layers. Therefore, it is difficult and expensive to increase the thickness of the conductive layer
9
formed on the side wall of the sacrificial insulating layer pattern
7
using traditional sputtering methods. Also, shown in
FIG. 2
is an insulating layer
11
for planarization. The insulating layer
11
for planarization fills a concave region on the contact plug
5
. The insulating layer
11
for planarization may be a CVD oxide layer which is formed over the entire surface of the semiconductor substrate over the conductive layer
9
.
Referring to
FIG. 3
, the insulating layer
11
for planarization is etched by a blanket etch-back process or a chemical mechanical polishing (CMP) process until the conductive layer
9
, formed over the entire surface of the semiconductor substrate over the sacrificial insulating layer pattern
7
, is exposed. After a sputter etching process, a cylindrical storage electrode
9
a
is formed, remaining only on the side wall and the bottom of the hole exposing the contact plug
5
. The inner surface and the outer surface of the vertical pillar for the cylindrical storage electrode
9
a
are also exposed by removing the insulating layer
11
for planarization remaining inside the storage electrode
9
a
and the sacrificial insulating layer pattern
7
. A high dielectric layer
13
and a plate electrode
15
are sequentially formed over the entire surface of the semiconductor substrate, including the inner surface and the outer surface of the vertical pillar for the cylindrical storage electrode
9
a
. When the high dielectric layer
13
is formed from either a Ta
2
O
5
layer, a BST layer, a PZT layer, or a PLZT layer, the high dielectric layer
13
must be thermally treated at a temperature of between about 550° C. to 750° C. to achieve crystallization. During the heat treatment, the grain of the cylindrical storage electrode
9
a
is grown, so that the cylindrical storage electrode
9
a
may be easily physically transformed. Such a phenomenon becomes severe as the thickness T
2
of the pillar of the cylindrical storage electrode
9
a
is reduced. As a result, cracks may form in the high dielectric layer
13
due to the physical transformation of the cylindrical storage electrode
9
a.
Accordingly, the cracks which are generated in the high dielectric film degrades the leakage current characteristic of the capacitor and reduces the capacitance. Furthermore, when a pre-treatment process such as a process of cleaning the surface of the cylindrical storage electrode is carried out before forming the high dielectric film, the very thin vertical pillar of the cylindrical storage electrode may be easily broken.
SUMMARY OF THE INVENTION
A feature of the present invention is to provide a capacitor having a storage electrode formed from a metal layer or a conductive material layer containing a metal that is resistant to transformation and breakage.
Another feature of the present invention is to provide a method for manufacturing a capacitor, as associated with the first feature of the present invention.
To achieve the first feature of the present invention, there is provided a capacitor comprising a storage electrode having at least two conductive layer patterns. The two conductive laye

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