Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-12-07
2003-01-28
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S396000, C438S393000, C438S250000, C438S397000, C438S254000
Reexamination Certificate
active
06511880
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a capacitor of a semiconductor device, and more particularly to, a capacitor of a semiconductor device capable of having high capacitance and reduced leakage current, and the method of manufacture thereof.
2. Description of the Related Art
As the memory cells of DRAM devices are increased, the areas allotted for each memory cell decreases. Therefore, memory cells are required to form a capacitor having a large capacitance to provide accurate data read while occupying a small area.
The capacitance of a capacitor is increased by using an insulating layer having a high dielectric constant as a dielectric layer or by enlarging the surface area of the capacitor. Recent highly-integrated DRAM semiconductor devices provide sufficient capacitance by using a TaON layer as the dielectric layer.
The conventional capacitor of a semiconductor device and the method of manufacture thereof will be described with reference to FIG.
1
.
FIG. 1
is a cross-sectional view showing a capacitor of a semiconductor device and the method of manufacture thereof according to the prior art.
Referring to
FIG. 1
, first, an interlayer insulating layer
3
is formed on a semiconductor substrate
1
having a transistor (not shown) thereon. The interlayer insulating layer is selectively removed, thereby forming a plug contact hole
5
to expose a part of the junction area of the transistor (not shown).
A doped polysilicon layer is deposited to be in contact with the exposed junction area (not shown) on the interlayer insulating layer
3
including the plug contact hole
5
. Then, a contact plug
7
is formed in the plug contact hole
5
by selectively removing the doped polysilicon layer.
Subsequently, a doped polysilicon layer is deposited and selectively patterned on the interlayer insulating layer
3
including the contact plug
7
to form a lower electrode
9
. The lower electrode
9
may be formed in a shape of a cylinder, pin or stack. The surface of lower electrode
9
is subjected to an in-situ plasma or HF cleaning process to prevent the formation of natural oxide layers.
TaON layers
11
are then formed on the surfaces of the lower electrode
9
and the interlayer insulating layer
3
as dielectric layers. The TaON layer
11
is formed by mutual surface chemical reaction between Ta chemical vapor, NH
3
gas and O
2
gas, wherein the Ta chemical vapor is obtained by evaporating a precursor such as Ta(OC
2
H
5
)
5
.
The TaON layer
11
is crystallized by performing a thermal treatment at a predetermined temperature.
Finally, an upper electrode
13
is formed on the upper part of the TaON layer
11
, thereby completing a capacitor of a semiconductor device. Here, the upper electrode
13
is formed with metal materials such as TiN, TaN, W, WN, Wsi, Ru, RuO
2
, Ir, IrO
2
and Pt.
In the resultant capacitor, the TaON layer
11
has a high dielectric constant of approximately 20 to 25, and at the same time, a low oxidation reaction property since it comprises a stable combination of Ta—O—N. Therefore, it is possible to prevent the generation of natural oxide layers and increase of thickness of the dielectric layer in the following thermal treatment.
However, a capacitor and the method of manufacture according to the conventional art have several problems due to the fact that the lower electrode is formed with a doped polysilicon layer.
As is well-known, the doped polysilicon layer has an improved oxidation reaction property. Therefore, the surface of lower electrode is naturally oxidized during the thermal treatment to crystallize the TaON layer, thereby causing the generation of natural oxide layers.
The natural oxide layers comprise SiO
2
having a low dielectric constant, thereby increasing the thickness of dielectric layer and lowering the dielectric property. As a result, capacitance is decreased.
A method has been proposed to decrease the thickness of the dielectric layer T
ox
, to solve the problems. However, according to this method, leakage current is increased and performance of the capacitor is lowered.
SUMMARY OF THE INVENTION
The present invention solves the above problems and has as an object to provide a capacitor of a semiconductor device capable of having high capacitance and reduced leakage current.
In order to accomplish this object, one embodiment of the present invention comprises the steps of: providing a semiconductor substrate; forming a lower electrode on the semiconductor substrate; forming a Ta—O—Sn layer on the lower electrode; and forming an upper electrode on the Ta—O—Sn layer.
Another embodiment present invention comprises the steps of: providing a semiconductor substrate; forming a lower electrode on the semiconductor substrate; forming a nitride layer on the lower electrode; forming an oxide tin layer on the nitride layer; forming an amorphous TaON layer on the oxide tin layer; diffusing oxygen and tin in the oxide tin layer and the amorphous TaON layer by thermal treatment process, thereby changing the layers into a Ta—O—Sn layer; and forming an upper electrode on the Ta—O—Sn layer.
Yet another embodiment of the present invention comprises the steps of: providing a semiconductor substrate; forming an interlayer insulating layer on the semiconductor substrate and selectively patterning the interlayer insulating layer to form a first contact hole; forming a contact plug in the first contact hole; forming a cap oxide layer on the interlayer insulating layer including the contact plug; selectively removing the cap oxide layer to expose the contact plug to form a second contact hole; forming a conductive material layer on the cap oxide layer including the second contact hole; selectively removing the conductive material layer until the cap oxide layer is exposed to form a low electrode; removing the cap oxide layer and forming a nitride layer on the resultant structure; forming an oxide tin layer on the upper part of the nitride layer; forming an amorphous TaON layer on the upper part of the oxide tin layer; diffusing oxygen and tin in the amorphous TaON layer and oxide tin layer by thermal treatment process, thereby changing the layers into a Ta—O—Sn layer; and forming an upper electrode on the upper part of the Ta—O—Sn layer.
Still another embodiment of a capacitor of the semiconductor device according to the present invention comprises: a semiconductor substrate; a lower electrode formed on the semiconductor substrate; a crystallized TaON layer formed on the lower electrode; a Ta—O—Sn layer formed on the crystallized TaON layer; and an upper electrode formed on the Ta—O—Sn layer.
REFERENCES:
patent: 4794302 (1988-12-01), Nire et al.
patent: 5589733 (1996-12-01), Noda et al.
patent: 6036823 (2000-03-01), Inoguchi et al.
patent: 6340622 (2002-01-01), Lee et al.
Hynix / Semiconductor Inc.
Kennedy Jennifer M.
Ladas & Parry
Niebling John F.
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