Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-01-20
2001-11-20
Smith, Matthew S. (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S240000, C438S256000, C438S398000
Reexamination Certificate
active
06319769
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, a capacitor in a semiconductor device and a fabricating method thereof.
2. Background of the Related Art
The size of cell areas is being reduced as a result of a semiconductor device's need for ultra-high integration. Thus, many techniques for increasing the capacitance of a capacitor are being developed. There are various ways of increasing the capacitance of a capacitor, such as forming a stacked or trench-type three dimensional structure, which increases a surface area of a dielectric layer.
The three dimensional stacked structure, which is easily fabricated and is suitable for mass production, increases the capacitance, and also provides immunity against alpha (&agr;) particles which cause information disturbance. A stacked capacitor is characterized by a doubly-stacked, fin-type or crown-type shape.
In order to form a cell during DRAM fabrication, transistors and the like are formed on a semiconductor substrate, storage and plate electrodes made of polycrystalline silicon and a dielectric layer are formed so that the dielectric layer lies between the electrodes, and metal interconnect lines are formed to connect the devices to one another.
The following related art techniques are used to increase the effective area of a capacitor for securing the capacitance of a capacitor in the limited space that is provided by a cell in a memory device.
First, the surface area of a capacitor, which is limited by design rules and structural limitations, can be increased by forming a storage electrode with a surface that has a rugged morphology. After a box-type storage electrode has been defined, a plurality of Hemispherical Silicon Grains (hereinafter abbreviated HSG) are formed on the surface of the storage electrode.
Second, the capacitance can be increased by forming a dielectric layer with a dielectric substance that has a relatively large dielectric constant, such as Ta
2
O
5
, BST(Ba
1
Sr
1−x
TiO
3
) or the like.
It would be desirable to combine the first and second techniques discussed above in order to secure the capacitance of a capacitor. Unfortunately, if a capacitor is formed with a dielectric layer of Ta
2
O
5
between a storage electrode of silicon and a plate electrode of metal such as TiN, which is called a metal-insulator-semiconductor (MIS) structure, the capacitance of the capacitor is reduced due to the increased thickness of the dielectric layer. The dielectric layer becomes thicker because an interface layer of Si—O—N is formed at the interface between the Ta
2
O
5
layer and the silicon layer. The capacitance of the capacitor is reduced because the capacitance is proportional to the surface area of a dielectric layer, but inversely proportional to the thickness of the dielectric layer. Thus, when a storage electrode having hemispherical protruding parts is formed with silicon, and a dielectric layer is formed with Ta
2
O
5
, it is hard to attain the intrinsic dielectric constant of the Ta
2
O
5
layer because to a new insulating layer, such as an oxide layer, is generated at a later step.
Another structure that allows the capacitance of a capacitor to be maximized is a MIM (metal-insulator-metal) structure, which uses metal for the storage electrode. The storage electrode is typically formed with W, WN, RuO
2
and the like.
However, a problem with the MIM structure is that it causes a large step difference between the cell area and the peripheral area as the height of the storage electrode of a conventional crown type or a stacked-flat type is increased due to the reduced capacitor area used in next-generation devices versus 256M DRAM.
FIG. 1
to
FIG. 3
show cross-sectional views of fabrication steps for a related art method of fabricating a semiconductor device. Referring to
FIG. 1
, an impurity region
11
, used as a source or drain region, is formed by heavily doping a predetermined portion of a p-type semiconductor silicon substrate
10
with n-type impurities, such as As, P or the like.
A silicon oxide insulating interlayer
12
is formed on the silicon substrate
10
by chemical vapor deposition(hereinafter abbreviated CVD). A contact hole that exposes a surface of the impurity region
11
is formed by removing a portion of the insulating interlayer
12
by photolithography. A conductive layer of W is formed on the insulating interlayer
12
by CVD to fill up the contact hole. A conductive plug
13
, which is connected electrically to the impurity region
11
and fills up the contact hole, is formed by etching back the conductive layer of W until a surface of the insulating interlayer
12
is exposed.
A polycrystalline silicon layer doped with impurities is deposited on the insulating interlayer
12
, including an exposed surface of the plug
13
, by CVD. Then, a storage electrode
14
is formed by patterning the polycrystalline silicon layer by photolithography and dry etching. In this case, the storage electrode
14
may be patterned into one of various shapes, such as a box, crown, cylinder, fin and the like.
Referring to
FIG. 2
, a plurality of hemispherical protruding parts
15
are selectively formed by carrying out a HSG formation step on an exposed surface of the storage electrode
14
using SiH
4
gas. As a result, a final storage electrode
14
and
15
is attained by the storage electrode
14
and the protruding parts
15
. The hemispherical protruding parts
15
are typically formed by flowing SiH
4
gas over the storage electrode
14
under the condition of a vacuum state that ranges from 1.0E(−7) to 5.0E(−8) Torr. This technique results in the deposition of hemispherical grains of polycrystalline silicon
15
on the storage electrode
14
. A surface of the final storage electrode
14
and
15
is treated by rapid thermal nitrization (hereinafter abbreviated RTN) under NH
3
ambience to improve the surface characteristics of the polycrystalline silicon
14
. In this case, a thin nitride film 10 Å thick (not shown) is formed on the silicon layer to prevent leakage current.
A dielectric layer
16
is formed by depositing Ta
2
O
5
, which has an excellent dielectric constant, on the final storage electrode
14
and
15
on which the nitride film is formed. Then, the characteristics of the dielectric layer
16
are improved by annealing the dielectric layer under oxygen ambience. This is done because the dielectric layer
16
, which consists of Ta
2
O
5−x
, needs to be saturated into Ta
2
O
5
to provide an ideal dielectric constant. Unfortunatley, the annealing step can cause formation of an Si—O—N layer between the storage electrode
14
/
15
and the dielectric layer
16
. In this case, as mentioned in the foregoing description, the Si—O—N layer at the interface between the silicon
14
and
15
and the Ta
2
O
5
layer
16
ruins the characteristics of the Ta
2
O
5
dielectric layer
16
.
Referring to
FIG. 3
, a plate electrode of metal
17
is formed by depositing TiN on the insulating layer
12
, including a surface of the dielectric layer
16
, thereby completing the fabrication of a capacitor. However, the method of fabricating a capacitor according to the related art has difficulty in forming a crown type storage electrode on which a dielectric layer of Ta
2
O
5
is formed due to dimensional limitations. For example, in DRAMs that are over 256M, the cell size is less than 0.25 &mgr;m. Further, the method of the related art ruins the characteristics of the dielectric layer due to the interface layer between the silicon
14
and
15
and Ta
2
O
5
layers
16
. In addition, the height of the storage electrode is over 1.3 &mgr;m when a box-type capacitor is formed, with the MIS structure having HSG or the MIM structure having a smooth surface. Thus, a step difference between cell and logic areas in a DRAM become large, which makes later processing steps difficult.
SUMMARY OF THE INVENTION
The present invention is directed to a capacitor in a semiconductor device and a fabri
Fleshner & Kim LLP
Hyundai Electronics Industries Co,. Ltd.
Malsawma Lex H.
Smith Matthew S.
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