Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-02-26
2002-10-01
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S785000, C257S310000
Reexamination Certificate
active
06458645
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor structures and methods for fabricating such structures in semiconductor integrated circuits and, in particular, to forming capacitors for memory cells having high dielectric constant materials therein.
BACKGROUND OF THE INVENTION
Dynamic random access memories (DRAMs) are the most widely used form of memory integrated circuits to date. DRAMs are composed of memory cell arrays and peripheral circuitry required for cell access and external input and output. Each memory cell array is formed of a plurality of memory cells for storing bits of data. Typical memory cells are formed of a capacitor, for storing electric charges and a transistor, for controlling charge and discharge of the capacitor. Of primary concern is maximizing the storage capacitance of each memory cell capacitor, particularly in light of the demand for 256 Mb DRAMs today and higher densities in the future without increasing the chip space required to form the array. There is a need to decrease the chip space required to form each memory cell while maximizing the capacitance of the memory cells. The importance of high density DRAMs cannot be overstated in today's competitive microelectronics market. Devices are becoming smaller, but they are required to provide much more performance.
One way to achieve greater capacitance per unit area is to roughen the surface of the capacitor plate, increasing the surface area. As can be seen from the following equation (I), the most important parameters involved in achieving maximum charge, Q, stored on the capacitor are the thickness of the capacitive dielectric film (t
cdf
), the area of the capacitor (A), and the dielectric constant (∈). The voltage applied across the capacitor plates is V.
Q
=(∈·
A·V
)/
t
cdf
(I)
Increasing the capacitor area (A) by forming the storage capacitor in a trench shape etched in the substrate is well known in the art, as well as using a stacked capacitor structure. Stacked-type capacitors feature a major part of the capacitor extending over the gate electrode and field isolating film of the underlying transistor. Such structures are generally composed of a lower plate electrode (consisting of a base portion and a standing wall portion), a capacitive dielectric film, and an upper plate electrode. Other complex topographical lower plate electrode configurations have also been used to maximize the capacitive area (A) of a memory cell, such as fin-type, double-sided, and roughened lower plate electrode structures produced using hemispherical grain (HSG) polysilicon.
In addition to increasing the capacitive surface area (A) of a memory cell, as can be seen from the above equation (I), the thickness of the capacitive dielectric film (t
cdf
) must be minimized to maintain the maximum charge stored on the capacitor. However, the capacitive dielectric film must also prevent direct electrical contact between the lower and upper electrodes to prevent the charge from decaying.
It is also desirable to utilize a capacitive dielectric film having as high of a dielectric constant (∈) as possible to further increase the capacitance per unit area of a memory cell. One material that has a high dielectric constant is tantalum oxide, such as tantalum penta oxide (Ta
2
O
5
). Ta
2
O
5
potentially has a dielectric constant (∈) of about 22, which is significantly greater than conventional silicon oxide, which has a dielectric constant (∈) of only about 3.9.
A capacitor of a memory cell formed with Ta
2
O
5
insulator includes an electrode. To attain adequate step coverage for the electrode on an integrated circuit, the electrode may be initially formed with an organometallic precursor that contains carbon.
After the capacitor is formed, the integrated circuit is subject to a high temperature processing step, such as borophosphosilicate glass (BPSG) reflow or polysilicon activation. During such heating, in the memory cell capacitor, carbon from the electrode diffuses into the Ta
2
O
5
insulator. The carbon in the Ta
2
O
5
insulator forms a leakage mechanism that renders the capacitor unusable. A relatively high leakage current flows through the capacitor even when relatively small voltage is applied across the capacitor. Therefore, there is a need for a capacitor that has a relatively high capacitance per unit area, to ensure high device density, and a relatively low leakage current. There is also a need for a dielectric material having a high dielectric constant that is substantially unaffected by subsequent high temperature processing steps.
SUMMARY OF THE INVENTION
A capacitor has a tantalum oxynitride film. One method for making the film comprises forming a bottom plate electrode and then forming a tantalum oxide film on the bottom plate electrode. Nitrogen is introduced to form a tantalum oxynitride film. A top plate electrode is formed on the tantalum oxynitride film. In another embodiment, an anti-fuse is formed in the same manner.
In one embodiment, the step of forming the tantalum oxide film comprises the steps of forming tantalum on the bottom electrode, and oxidizing the tantalum. In another embodiment, tantalum oxide film is formed by chemical vapor deposition with tantalum and oxygen sources. In yet another embodiment, the tantalum oxide film is annealed to form a tantalum oxynitride film Ta
x
N
y
O
z
, wherein (y+z)/x>2.5.
In another embodiment, the method of forming the capacitor includes the step of forming a bottom plate electrode. A tantalum oxynitride film is formed on the bottom plate electrode. A top plate electrode is formed on the tantalum oxynitride film. In one embodiment, the tantalum oxynitride film is formed by metal organo chemical vapor deposition with a nitrogen source that is hydrazene at a temperature between approximately 400 and 600 degrees Celsius so as to form amorphous tantalum oxynitride.
In another embodiment, the invention is a capacitor that has a bottom plate electrode, a tantalum oxynitride film and a top plate electrode. In one embodiment, the tantalum oxynitride film is amorphous.
In one embodiment, the capacitor may be used in a memory array of a memory. The memory comprises the memory array, a control circuit, operatively coupled to the memory array, and address logic, operatively coupled to the memory array and the control logic.
In yet another embodiment, the capacitor may be used in the memory array of a system. The system comprises a memory and a processor coupled to the memory.
In yet a further embodiment, an antifuse is operated by applying a voltage across the electrodes of the capacitor having a tantalum oxynitride film. A hole is formed in the tantalum oxynitride film.
It is an advantage of the present invention that the capacitor has a high dielectric constant. It is also a benefit of the present invention that it is less affected by heat so as to have reduced leakage current. It is a further advantage of the invention that the capacitor has enhanced reliability.
REFERENCES:
patent: 4084986 (1978-04-01), Aoki et al.
patent: 5111355 (1992-05-01), Anand et al.
patent: 5142438 (1992-08-01), Reinberg et al.
patent: 5352623 (1994-10-01), Kamiyama
patent: 5362632 (1994-11-01), Mathews
patent: 5585301 (1996-12-01), Lee et al.
patent: 5677015 (1997-10-01), Hasegawa
Wolf, S.; Tauber, R.N.; “Silicon Processing for the VLSI Era”; vol. 1; Lattice Press; Sunset Beach, Ca.; 1986; pp. 57-58, 194.*
Fazan, P.C., et al., “A High-C Capacitor (20.4 fF/um2) with Ultrathin CVD—Ta2O5 Films Deposited on Rugged Poly-Si for High Density DRAMs”,Int'l Electron Devices Meeting: Technical Digest, San Francisco, CA, 263-266, (Dec. 1992).
Fazan, P.C., et al., “Ultrathin Ta2O5 Films on Rapid Thermal Nitrided Rugged Polysilicon for High Density DRAMs”,Extended Abstracts: Int'l Conference on Solid State Devices and Materials, Tsukuba, 697-698, (Aug. 1992).
Al-Shareef Husam N.
DeBoer Scott Jeffrey
Gealy Dan
Thakur Randhir P. S.
Berezny Neal
Fourson George
Schwegman Lundberg Woessner & Kluth P.A.
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