Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1997-11-21
2001-07-03
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S306000, C257S310000
Reexamination Certificate
active
06255688
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to integrated circuits and, more specifically, to an integrated circuit that includes an embedded dynamic random access memory having a capacitor associated therewith.
BACKGROUND OF THE INVENTION
Integrated circuits in general, and CMOS devices in particular, have continued to gain wide spread usage as user demands for increased functionality and enhanced benefits continues to increase. In order to meet this demand, the integrated circuit industry continues to decrease the size of circuit structures in order to place more circuits in the same size integrated circuit area thereby continuously increasing the packing density for a given chip size. Over the last several years, structures have gone from 1.2 micron gate areas (1 Meg capacity) in the past, down to gate structure areas of 0.25 microns (256 Meg capacity) currently and promise to become even smaller in the near future.
The ever increasing demand for computer memory to facilitate calculations and data storage have fostered intense development efforts in the area of Dynamic Random Access Memory (DRAM). The DRAM is generally a collection of transistor devices with each having an integrated circuit capacitor typically connected to its source electrode thereby forming a memory cell. This collection of memory cells is then arranged into a memory structure using a word line and a bit line to address each memory cell. This integrated capacitor may store an electrical charge to represent a logical “1” or store no electrical charge for a logical “0” as instructed by the word and bit control lines.
Construction of these memory capacitors consists of using typically a tungsten (W) plug structure for 0.25 micron technology connected to the source of the transistor, which then supports a barrier layer, a bottom electrode, a dielectric material, such as tantalum pentoxide and then a top electrode in sequence.
As the size technology of CMOS devices continues to shrink, the structure for a given memory size or circuit capability also shrinks as noted above. However, the bond pads which allow the integrated circuit to connect to external circuitry cannot continue to shrink indefinitely. Currently, an integrated circuit package may have about 200 bond pads that are 50 microns by 50 microns in size. Shrinking topology coupled with this bond pad lower limitation results in an excess of empty space around the bond pads. This allows for the inclusion of additional embedded memory around the bond pads.
In an attempt to add the above-mentioned memory in certain conventional CMOS technologies, some manufacturers have used titanium (Ti) to form a barrier layer with a titanium nitride (TiN) lower electrode in conjunction with the use of tantalum pentoxide (Ta
2
O
5
) as the dielectric layer of the capacitor. Unfortunately, however, in these cases, the edges of the Ti/TiN is exposed and in contact with the Ta
2
O
5
which causes the Ti to chemically reduce the Ta
2
O
5
creating electrical leakage paths or shorts. This results in general circuit performance degradation or failure.
Accordingly, what is needed in the art is a CMOS structure and a process of fabrication therefore in which embedded memory can be added without substantial changes in the fabrication processes typically used to manufacture CMOS technologies.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides for use with an integrated circuit, an embedded memory having a transistor in contact with an interconnect formed within a dielectric layer overlaying the transistor. In one embodiment, the embedded memory comprises a capacitor located on the dielectric layer that contacts the interconnect. In this particular embodiment, the capacitor includes a first electrode located on the interconnect wherein the first electrode is a layer of aluminum, aluminum alloy or titanium nitride and substantially free of a titanium layer. In one advantageous embodiment, the first electrode layer is an aluminum alloy. Moreover, the thickness of the first electrode may, of course, vary depending on the design. However, in one particular embodiment, the first electrode may have a thickness ranging from about 10 nm to about 50 nm.
Thus, the present invention provides an embedded memory structure having a capacitor associated therewith wherein the metals within the electrodes do not chemically react with the capacitor dielectric in such a way as to degrade the dielectric or cause general degradation of the device. As previously mentioned, some prior art materials chemically reacted with the capacitor dielectric by reducing the dielectric, which in turn, caused leakage within the device and ultimately device failure.
In the present invention, the capacitor further includes a capacitor dielectric located on the first electrode, which is subject to reduction by titanium. For example, in one embodiment, the capacitor dielectric may be tantalum pentoxide. Additionally, the capacitor includes a second electrode located on the capacitor dielectric.
In those embodiments where the first electrode is an aluminum alloy, the aluminum alloy may include copper. In yet another embodiment, the first electrode layer may be titanium nitride.
In another embodiment, the first electrode includes a barrier layer in contact with the interconnect. The barrier layer serves to prevent or inhibit cross diffusion of diverse materials. In such embodiments, the barrier layer may be comprised of aluminum alloy. In yet other embodiments, the barrier layer may be titanium nitride wherein the titanium has a thickness less than 30 nm.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
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patent: 3781610 (1973-12-01), Bodway
patent: 3819990 (1974-06-01), Hayashi et al.
patent: 5104826 (1992-04-01), Fujita et al.
patent: 5335138 (1994-08-01), Sandhu et al.
patent: 5641994 (1997-06-01), Bollinger et al.
patent: 5656536 (1997-08-01), Wu
patent: 5837593 (1998-11-01), Park et al.
patent: 5970309 (1999-10-01), Ha et al.
patent: 4-43674 (1992-02-01), None
Lee Kuo-Hua
Merchant Sailesh M.
Agere Systems Guardian Corp.
Eckert II George C.
Lee Eddie C.
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