Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-01-02
2004-09-07
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S250000, C438S393000, C438S396000, C438S003000, C257S295000, C257S303000, C257S310000
Reexamination Certificate
active
06787414
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a capacitor for semiconductor memory device and a method of manufacturing the same, and more particularly to a capacitor for semiconductor memory device capable of increasing the storage capacitance as well as preventing leakage current and a method of manufacturing the same.
BACKGROUND OF THE INVENTION
As the number of memory cells composing DRAM semiconductor device has been recently increased, occupancy dimension of each memory cell is gradually decreased. Meanwhile, capacitors formed in the respective memory cells require a sufficient capacitance for precise reading out of storage data. Accordingly, the current DRAM semiconductor device requires memory cells in which capacitors having larger capacitance as well as occupying small area is formed. The capacitance of a capacitor can be increased by using an insulator having high dielectric constant as a dielectric layer, or by enlarging the surface area of a lower electrode. In a highly integrated DRAM semiconductor device, a Ta
2
O
5
layer having a higher dielectric constant than that of the nitride-oxide (NO) is now used as a dielectric, thereby forming a lower electrode of a 3-Dimentional structure.
FIG. 1
is a cross-sectional view showing a capacitor for conventional semiconductor memory device. Referring to
FIG. 1
, a gate electrode
13
including a gate insulating layer
12
at a lower portion thereof is formed according to a known technique on the upper part of a semiconductor substrate
10
which a field oxide layer
11
is formed at a selected portion thereof. A junction region
14
is formed on the semiconductor substrate
10
at both sides of the gate electrode
13
, thereby forming an MOS transistor. A first interlevel insulating layer
16
and a second interlevel insulating layer
18
are formed on the upper part of the semiconductor substrate
10
in which the MOS transistor is formed. A storage node contact hole h is formed inside the first and the second interlevel insulating layers
16
,
18
so that a junction region
14
is exposed. A cylinder type lower electrode
20
is formed according to a known method, inside the storage node contact hole h so as to be in contact with the exposed junction region
14
. A HSG (hemi-spherical grain) layer
21
is formed on a surface of a lower electrode
20
to increase the surface area of the lower electrode
20
more. Afterwards, a rapid thermal nitridation (RTN) process is performed on the surface of the lower electrode
20
which the HSG layer
21
is formed thereon by ex situ to prevent generation of a natural oxidation layer. Next, a first Ta
2
O
5
layer is formed on an upper part of the lower electrode
20
that is treated by the RTN process at temperature of approximately 400~450° C. to the thickness of 53~57 Å. Afterwards, an annealing step is performed at a low temperature, and then a second Ta
2
O
5
layer is formed to the same process and same thickness as those of the first Ta
2
O
5
layer. Sequentially, annealing steps at low and high temperatures are performed in series, thereby forming the Ta
2
O
5
layer
23
. Afterwards, to crystallize the Ta
2
O
5
layer
23
, the layer
23
is thermal-treated again at a selected temperature. An upper electrode
25
is formed of a polysilicon layer or metal layer doped on the Ta
2
O
5
layer
23
and made of a doped polysilicon layer or a metal layer.
However, a difference in the composition rate of Ta and O is occurred since the Ta
2
O
5
layer
23
generally has unstable stoichiometry. As a result, substitutional Ta atoms, i.e. vacancy atoms are generated in a thin film. Since those vacancy atoms are oxygen vacancies, leakage current is occurred.
Now, the Ta
2
O
5
layer is oxidized so as to remove the substitutional Ta atoms therein in order to stabilize the unstable stoichiometry thereof. However, the following problems are caused when the Ta
2
O
5
layer is oxidized to prevent leakage current. That is, the Ta
2
O
5
layer has great oxidation reactivity with the lower and the upper electrodes formed of polysilicon or TiN. Accordingly, during the oxidation process for oxidizing the substitutional Ta atoms, an oxide layer having low dielectric constant is formed at an interface by reaction between the Ta
2
O
5
layer and the lower electrode or the upper electrode. And, oxygen moves to the interface between the Ta
2
O
5
layer and the lower electrode, thereby deteriorating homogeneity in the interface.
Further, due to the reaction between an organic substance such as Ta(OC
2
H
5
)
5
used as a precursor and O
2
(or N
2
O) gas, impurities such as carbon atoms C, carbon compounds(CH
4
, C
2
H
4
) and H
2
O are generated in the Ta
2
O
5
layer. Those impurities increase leakage current in the capacitor and deteriorate the dielectric characteristics of the Ta
2
O
5
layer. Accordingly, a capacitor of great capacitance is difficult to obtain.
Moreover, the method using the Ta
2
O
5
layer as a dielectric layer requires an extra ex-situ process before the formation of the Ta
2
O
5
layer and after the cleaning step. Also, the Ta
2
O
5
layer should be deposited in double steps and two thermal processes at low and high temperatures should be performed after the deposition. Therefore, manufacturing process is cumbersome.
SUMMARY OF THE INVENTION
Accordingly, it is one object of the present invention to provide a capacitor for semiconductor device with a dielectric layer having low leakage current and high dielectric constant.
Furthermore, the other object of the present invention is to provide a method of manufacturing a capacitor for semiconductor device capable of simplifying manufacturing process thereof.
To achieve the foregoing objectives, the present invention according to one aspect includes: a lower electrode; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer, wherein the dielectric layer is a TiON layer.
Further, the present invention according to another aspect provides a method of manufacturing the capacitor of a semiconductor memory device including the steps of: forming a lower electrode on a semiconductor substrate; depositing a TiON layer as a dielectric layer on the lower electrode; and forming an upper electrode on the TiON layer.
The present invention according to still another aspect provides a method of manufacturing the capacitor of a semiconductor memory device including the steps of: forming a lower electrode on a semiconductor substrate; surface-treating to prevent a natural oxide layer from generating on the surface of the lower electrode; depositing a TiON layer on the lower electrode using an organic Ti metal precursor; thermal-treating the TiON layer; and forming an upper electrode on the TiON layer, wherein the TiON layer is formed by chemical vapor reaction of Ti chemical vapor, NH
3
gas and O
2
gas in the LPCVD chamber maintained at temperature of 300 to 600
C, wherein the Ti chemical vapor is an evaporated organic Ti metal precursor.
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Hyundai Electronics Industries
Kennedy Jennifer M.
Niebling John F.
Pillsbury & Winthrop LLP
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