Capacitor for semiconductor memory device and method of...

Details Capacitor for semiconductor memory device and method of... Capacitor for semiconductor memory device and method of...

2000-06-30

2002-09-10

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S785000

Reexamination Certificate

active

06448128

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a capacitor for semiconductor memory device and a method of manufacturing the same, and more particularly to a capacitor for semiconductor memory device capable of increasing the storage capacitance as well as preventing leakage current and a method of manufacturing the same.
BACKGROUND OF THE INVENTION
As the number of memory cells composing DRAM semiconductor device has been recently increased, occupancy area of each memory cell is gradually decreased. Meanwhile, capacitors formed in the respective memory cells require a sufficient capacitance for precise reading out of storage data. Accordingly, the current DRAM semiconductor device requires memory cells in which capacitors having larger capacitance as well as occupying small area are formed. The capacitance of a capacitor can be increased by using an insulator having high dielectric constant as a dielectric layer, or by enlarging the surface area of a lower electrode. In a highly integrated DRAM semiconductor device, a Ta
2
O
5
layer having a higher dielectric constant than that of the nitride-oxide(NO) is now used as a dielectric, thereby forming a lower electrode of a 3-Dimentional structure.
FIG. 1
is a cross-sectional view showing a capacitor for a conventional semiconductor memory device. Referring to
FIG. 1
, a gate electrode
13
including a gate insulating layer
12
at a lower portion thereof is formed according to a known technique on the upper part of a semiconductor substrate
10
which a field oxide layer
11
is formed at a selected portion thereof. A junction region
14
is formed on the semiconductor substrate
10
at both sides of the gate electrode
13
, thereby forming an MOS transistor. A first interlayer insulating layer
16
and a second interlayer insulating layer
18
are formed on the upper part of the semiconductor substrate
10
which the MOS transistor is formed therein. A storage node contact hole h is formed inside the first and the second interlayer insulating layers
16
,
18
so that the junction region
14
is exposed. A cylinder type lower electrode
20
is formed according to a known method, inside the storage node contact hole h so as to be in contact with the exposed junction region
14
. A HSG(hemi-spherical grain) layer
21
is formed on a surface of a lower electrode
20
to increase the surface area of the lower electrode
20
more. A tantalum oxide layer
23
is formed on the surface of the HSG layer
21
. Afterwards, the Ta
2
O
5
layer
23
is deposited on the upper part of the lower electrode
20
including the HSG layer
21
by using an organic metal precursor such as Ta(OC
2
H
5
)
5
. Afterwards, the Ta
2
O
5
layer
23
is thermal-treated at a selected temperature so as to crystallize. An upper electrode
25
is formed of a polysilicon layer or a metal layer doped on the upper part of the Ta
2
O
5
layer
23
.
However, a difference in the composition rate of Ta and O is generated since the Ta
2
O
5
layer
23
generally has unstable stoichiometry. As a result, substitutional Ta atoms, i.e. vacancy atoms are generated in a thin film. Since those vacancy atoms are oxygen vacancies, leakage current is generated.
Now, a process for oxidizing the Ta
2
O
5
layer has been additionally performed to remove the substitutional Ta atoms therein. However, when performing this oxidizing process, an oxide reaction of the Ta
2
O
5
layer with the upper and the lower electrodes actively progresses. As a result, an oxide layer having a low dielectric constant is formed on the interface between the Ta
2
O
5
layer and the lower electrode or the upper electrode, thereby deteriorating the homogeneity of the interface and increasing the thickness of an effective oxide layer as well as manufacturing process steps.
Moreover, since the Ta
2
O
5
layer is formed by a reaction between an organic tantalum precursor containing carbon components and oxygen, reaction impurities such as carbon atoms (C), carbon compounds(CH
4
, C
2
H
4
), and H
2
O remain therein after the deposition process. These reaction by-products cause leakage current and deteriorate the dielectric strength of the Ta
2
O
5
layer.
To remove these reaction by-products, the Ta
2
O
5
layer has been conventionally deposited more than 2 layers, at least. And, after each deposition step, a plasma treatment or UV—O
3
process has been additionally performed to remove reaction by-products inside the Ta
2
O
5
layer. However, the above method has a demerit of increase in the number of the processes.
SUMMARY OF THE INVENTION
Accordingly, it is one object of the present invention to provide a capacitor for a semiconductor memory device with a dielectric layer having low leakage current and high dielectric constant.
Furthermore, the other object of the present invention is to provide a method of manufacturing a capacitor for a semiconductor memory device capable of simplifying manufacturing process thereof.
To achieve the foregoing objectives, a capacitor for a semiconductor memory device of the present invention according to one aspect includes: a lower electrode; a dielectric layer formed on the lower electrode; and an upper electrode formed on the upper part of the dielectric layer, wherein the dielectric layer is a (TaO)
1-x
(TiO)N layer.
Further, the present invention according to another aspect provides a method of manufacturing a capacitor of a semiconductor memory device including the steps of: forming a lower electrode on the semiconductor substrate; depositing a (TaO)
1-x
(TiO)N layer as a dielectric layer on the upper part of the lower electrode; and forming an upper electrode on the upper part of the (TaO)
1-x
(TiO)N layer.
And, the present invention according to still another aspect provides a method of manufacturing a capacitor of a semiconductor memory device including the steps of: forming a lower electrode on the semiconductor substrate; surface-treating to prevent a natural oxide layer from generating on the surface of the lower electrode; depositing the (TaO)
1-x
(TiO)N layer as a dielectric on the upper part of the lower electrode; diffusing and simultaneously crystallizing impurities inside the (TaO)
1-x
(TiO)N layer; and forming an upper electrode on the upper part of the (TaO)
1-x
(TiO)N layer, wherein the (TaO)
1-x
(TiO)N layer is formed by a surface chemical reaction of Ta chemical, Ti chemical vapor, NH
3
gas and O
2
gas in an LPCVD chamber maintaining a temperature of 300 to 600° C.


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