Capacitor for highly-integrated semiconductor memory devices...

Details Capacitor for highly-integrated semiconductor memory devices... Capacitor for highly-integrated semiconductor memory devices...

2001-12-27

2003-12-02

Fahmy, Wael (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S255000, C438S396000

Reexamination Certificate

active

06656789

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory and, more particularly, to a capacitor in a semiconductor device and a method of fabricating a capacitor suitable for a highly-integrated memory device using a TaON dielectric layer having a high dielectric constant.
2. Background of the Related Art
As the degree of integration of memory products increases with the development of fine linewidth semiconductor technology, the unit memory cell area has been greatly reduced and the operating voltages have been decreased.
In spite of this reduction in cell area, the charging capacitance necessary for proper memory device operation has remained at least 25 fF/cell so as to prevent the generation of soft errors and avoid the need to reduce the refresh time.
In a conventional DRAM capacitor utilizing a nitride/oxide (“NO”)layer structure as a dielectric, the configuration of the lower electrode may be modified to provide a complex three-dimensional structure or increase the height of the lower electrode. These structural modifications serve to increase the effective surface area and thereby provide the necessary charge capacitance.
However, the range of three-dimensional lower electrode configurations is limited by process difficulties. Moreover, increasing the lower electrode height produces a step height difference between the cell areas and the peripheral circuit areas. Eventually, increasing the step height difference will degrade the yield and reliability of the resulting devices, as a result of difficulties in forming conductors due to difficulties in obtaining a sufficient depth of focus during subsequent photolithographic processes.
Therefore, capacitors having conventional NO dielectric structures cannot be manufactured with both sufficient charge capacitance and cell area required for next generation DRAM devices having 256M or more memory cells.
Lately, developments of Ta
2
O
5
capacitors, which use Ta
2
O
5
films having dielectric constants ranging 25 to 27, instead of NO films having dielectric constants ranging 4 to 5, have been made to overcome the short comings of NO capacitors.
Ta
2
O
5
films, however, have an unstable chemical stoichiometric ratio, which results in Ta atoms in the film that are not fully oxidized due to differences in the composition ratio between the Ta and O atoms. Namely, it is inevitable that substitution type Ta atoms of an oxygen vacancy type exist locally in the film due to the unstable chemical composition ratio of the material itself.
Although the number and density of the oxygen vacancies in the Ta
2
O
5
film may vary in accordance with the ratio of the components and their bonding degree, oxygen vacancies can not be avoided completely.
Therefore, in order to prevent current leakage of a capacitor, an additional oxidation process is required to oxidize the substitution type Ta atoms present in the dielectric film to produce a more stable stoichiometric ratio throughout the Ta
2
O
5
film.
Moreover, the Ta
2
O
5
film has a high oxidation reactivity with polysilicon and TiN, materials that are commonly used to form the upper and/or lower electrodes of the capacitor. This reaction tends to form a low dielectric oxide layer and greatly reduce the homogeneity at an interface as oxygen in the Ta
2
O
5
film migrates to the interface and reacts with the electrode material.
Further, when the Ta
2
O
5
film is formed, carbon atoms and carbon compounds such as CH
4
, C
2
H
4
and the like, and H
2
O are produced by the reaction between the organic portions of the organometallic Ta(OC
2
H
5
)
5
precursor and the O
2
or N
2
O gas used to form the Ta
2
O
5
film and are incorporated into the film as impurities.
Consequently, oxygen vacancies, as well as carbon atoms, ions, and radicals exist in the Ta
2
O
5
film as impurities and increase the leakage current of the resulting capacitors and degrade their dielectric characteristics.
A proposed solution to these problems is a post-formation thermal treatment (oxidation) using an electrical furnace or RTP and a N
2
O or O
2
ambient to overcome these problems.
However, the post-formation thermal treatment in the N
2
O or O
2
ambient may increase the depth of the depletion layer since an oxide layer having a low dielectric constant is formed at the interface with the lower electrode.
Regarding the problems resulting from the post-formation thermal treatment and the subsequent formation of a contact plug for storing electric charges and a dielectric layer, a capacitor in a semiconductor device and a conventional method of fabrication are explained below with reference to
FIGS. 1-3
.
FIGS. 1 and 2
show cross-sectional views of a capacitor in a semiconductor device and a fabrication method thereof according to a conventional method.
Referring to
FIG. 1
, an insulating interlayer
3
, a barrier nitride layer
5
, and a buffer oxide layer
7
are sequentially deposited on a semiconductor substrate
1
. In this case, the insulating interlayer
3
is preferably formed by depositing HDP, BPSG, or SOG materials. The barrier nitride layer
5
is preferably formed using a plasma nitride deposition and the buffer oxide layer
7
is preferably deposited using PE-TEOS.
An upper surface of the buffer oxide layer
7
is then coated with a photoresist pattern (not shown in the drawing) for a plug contact mask. Using the photoresist pattern as a mask, contact holes
9
are then formed by removing portions of the buffer oxide layer
7
, the barrier nitride layer
5
, and the insulating interlayer
3
to expose portions of the semiconductor substrate
1
.
The photoresist pattern (not shown in the drawing) is then removed and a polysilicon material is deposited on the wafer. The polysilicon fills the contact holes
9
and forms a layer on the upper surface of the buffer oxide
7
. Contact plugs
11
are then formed by selectively removing the polysilicon material from the buffer oxide
7
by blanket etch.
Referring to
FIG. 2
, a cap oxide layer
13
is then deposited on an exposed upper surface of the entire structure including the contact plugs
11
.
After the cap oxide layer
13
has been coated with a photoresist pattern (not shown in the drawing) for a storage node mask, upper surfaces of the contact plugs
11
are exposed by selectively removing the cap oxide layer
13
using the photoresist pattern as an etch mask.
A doped polysilicon layer
15
is then deposited on the exposed surface of the cap oxide layer
13
and the exposed upper surface of the contact plugs
11
.
Referring to
FIG. 2
, lower electrodes
15
a
are formed by selectively removing the doped polysilicon layer
15
with blanket etch until the cap oxide layer
13
is exposed. A TaON or Ta2O5 dielectric layer
17
is then formed on an upper surface of the entire structure including the lower electrodes
15
a.
A thermal treatment is then performed on the TaON or Ta
2
O
5
dielectric layer
17
in an ambient of N
2
O or O
2
.
Finally, an upper electrode
19
is formed on the TaON or Ta
2
O
5
dielectric layer
17
to complete the capacitor fabrication.
As mentioned above, the contact plug
11
for a lower electrode contact in a capacitor in a semiconductor device using a TaON or Ta
2
O
5
dielectric as shown in
FIG. 1
, is formed by sequentially depositing the insulating interlayer (an oxide layer existing between the bit lines and the lower electrodes, which is not shown in the drawing), a barrier nitride layer, and an oxide buffer layer. These layers are then selectively removed to form an opening, a layer of conductive material is deposited, and the portion of the conductive layer that is not inside the opening removed area is removed to leave contact plugs.
Unfortunately, when the contact plugs are formed in such a manner, as shown in
FIG. 2
, the contact plugs
11
protrude out over the barrier nitride layer
5
by about 500 to 1500 Å. This tends to reduce the area occupied by the lower electrodes and cause electrical degradation and reliability problems as a result of the i

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