Capacitor for a semiconductor memory device

Details Capacitor for a semiconductor memory device Capacitor for a semiconductor memory device

1999-08-09

2001-09-04

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S303000

Reexamination Certificate

active

06285053

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 98-32237, filed on Aug. 7, 1998, the content of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a method for fabricating capacitors in a DRAM device.
2. Background of the Invention
Modern VLSI technology allows integration of 4 Giga bit DRAM, which requires the feature length of the device dimension to be less than 0.15 &mgr;m. Also, the contact hole size and the mis-alignment margin has to be reduced. The self-aligned contact process has been developed to reduce the contact hole size and to increase the degree of alignment in photolithography. The self-aligned contact process also reduces the contact resistance because the whole contact area is effective regardless of the reduction of the contact hole size.
The conventional process of fabricating capacitors in a semiconductor device will be described with reference to
FIGS. 1A
to
1
D, as follows:
Referring to
FIG. 1A
, a semiconductor substrate
10
is firstly provided with shallow trench isolations
12
to define active and inactive regions, and then covered with a first oxide layer
14
. The first oxide layer
14
is selectively etched according to a contact hole patterning mask to form the self-aligned contact holes for storage node contact pads
16
. The storage node contact pads
16
are formed by planarizing a polysilicon layer deposited over the substrate by CMP (Chernical-Mechanical Polishing) until the first oxide layer
14
is exposed. Thus, the storage node contact pad
16
is electrically connected to the substrate
10
. Subsequently, a second oxide layer
18
is deposited over the first oxide layer
14
embedding the storage node contact pads
16
as shown in
FIG. 1B
, then etched according to a bit line contact hole patterning mask to form bit line contact holes (not shown in the drawings). A polysilicon layer is deposited over the second oxide layer
18
, then etched until the second oxide layer
18
is exposed to form bit line contact pads (not shown in the drawings). Additionally formed on the second oxide layer
18
are the bit lines
20
electrically connected to the bit line contact pads. The second oxide layer
18
and the bit lines
20
are covered sequentially with a third oxide layer
22
, a nitride layer
24
and a fourth oxide layer
26
. In this case, the nitride layer
24
serves to protect the bit lines
20
from being oxidized by O
2
contained in the dielectric layer of the capacitor produced in the subsequent process steps.
Referring to
FIG. 1C
, storage node contact holes
27
are formed by sequentially etching the fourth oxide layer
26
, nitride layer
24
, third oxide layer
22
and second oxide layer
18
according to a storage node contact patterning mask until the upper surfaces of the storage node contact pads
16
are exposed. Referring to
FIG. 1D
, a polysilicon layer is deposited over the fourth oxide layer
26
containing the storage node contact holes
27
. This polysilicon layer is patterned according to a storage node patterning mask to form the storage nodes
30
integrated with the storage node contacts
28
. The storage node
30
is formed with a thickness of more than 10000Å. Finally, sequentially deposited over the fourth oxide layer containing the storage nodes
30
are the dielectric layer
32
and the upper electrode
34
of the capacitor.
With the increase in integration size, i.e., the number of transistors and other electronic components packed onto a single IC chip, the misalignment margin is reduced to less than 40 nm between the self-aligned contact pad and storage node contact, storage node contact and storage node, storage node contact and bit line, and storage node contact and gate. Moreover, metallization after forming the storage nodes should suffer considerably reduced margins for DOF (Depth of Focus) due to the level difference of more than 10000Å between the cell and core.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method of fabricating capacitors capable of reducing current leakage in a semiconductor device.
According to an aspect of the present invention, a method of fabricating capacitors in a semiconductor substrate with a first insulating layer deposited thereon, comprises the steps of etching the first insulating layer to simultaneously form first and second self-aligned contact pads electrically connected with the substrate, depositing a second insulating layer over the first insulating layer, forming bit lines on the second insulating layer with the upper and side surfaces of the bit lines being enclosed by an insulating material having an etching selectivity to the second insulating layer, forming a landing pad between the bit lines to be electrically connected with the first self-align contact pad, the landing pad having the maximum size within such range as not to connect with the second self-aligned contact pad, depositing a third insulating layer over the substrate with a thickness large enough to provide a desired capacitance, etching the third insulating layer according to a storage node contact hole patterning mask until exposing the upper surface of the landing pad so as to form a storage node contact hole, depositing a first conductive layer on the surfaces of the storage node contact hole, and sequentially depositing a capacitor dielectric layer and a second conductive layer over the third insulating layer and first conductive layer.
According to another aspect of the present invention, there is provided a capacitor formed in a semiconductor substrate, which comprises gate electrodes formed on the substrate so as to be enclosed by an insulating material, first and second self-aligned contact pads formed between the gate electrodes so as to electrically connect with substrate, a landing pad deposited on the first self-aligned contact pad to overlap the insulating material on the gate electrode, and storage nodes formed on both sides of a contact hole in an insulating layer deposited on the substrate so as to electrically connect with the landing pad, wherein the landing pad has the maximum size within such a range as not to connect with the second self-aligned contact pad.


REFERENCES:
patent: 5329146 (1994-07-01), Soeda
patent: 5392189 (1995-02-01), Fazan et al.
patent: 5869860 (1999-02-01), Widmann et al.
patent: 5981369 (1999-11-01), Yoshida et al.
patent: 6010943 (2000-01-01), Liao
patent: 6071773 (2000-06-01), Lee et al.
patent: 6124182 (2000-09-01), Tu et al.
patent: 362249473 (1987-10-01), None

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