Capacitor fabrication process for analog flash memory devices

Details Capacitor fabrication process for analog flash memory devices Capacitor fabrication process for analog flash memory devices

2000-07-11

2002-12-03

Chaudhuri, Olik (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S264000, C438S266000, C438S259000

Reexamination Certificate

active

06489200

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a method of fabricating an integrated circuit, and more particularly, to a method of fabricating capacitors for analog flash memory devices.
Industry has used or proposed a variety of memory devices. An example of such a memory device is an erasable programmable read-only memory (“EPROM”) device. The EPROM device is both readable, writable, and erasable, i.e., programmable. The EPROM is implemented using a floating gate field effect transistor, which has certain binary states. That is, a binary state is represented by the presence or absence of charge on the floating gate. The charge is generally sufficient to prevent conduction even when a normal high signal is applied to the gate of the EPROM transistor.
A wide variety of EPROMs is available. In a traditional form, EPROMs are programmed electrically and erased by exposure to ultraviolet light. These EPROMs are commonly referred to as ultraviolet erasable programmable read-only memories (“UVEPROM”s). UVEPROMs can be programmed by running a high current between a drain and a source of the UVEPROM transistor while applying a positive potential to the gate. The positive potential on the gate attracts energetic (i.e., hot) electrons from the drain-to-source current, where the electrons jump or inject into the floating gate and become trapped on the floating gate.
Another form of EPROM is the electrically erasable programmable read-only memory (“EEPROM” or “E2PROM”). EEPROMs are often programmed and erased electrically by way of a phenomenon known as Fowler-Nordheim tunneling. Still another form of EPROM is a “Flash EPROM,” which is programmed using hot electrons and erased using the Fowler-Nordheim tunneling phenomenon. Flash EPROMs can be erased in a “flash” or bulk mode in which all cells in an array or a portion of an array can be erased simultaneously using Fowler-Nordheim tunneling, and are commonly called “Flash cells” or “Flash devices.”
The flash memory devices generally include two polysilicon layers: a first polysilicon layer which defines a floating gate, and a second polysilicon layer which defines a control gate. The first polysilicon is lightly doped, and the second polysilicon is heavily doped. These polysilicon layers are appropriate for use as the electrodes of charge-storage capacitors since the lightly doped first polysilicon layer provides stable capacitance.
However, the lightly doped polysilicon layer is not suitable as an electrode of an analog capacitor because of its insufficient linearity. Analog circuits require linear analog capacitors for precision circuits such as switched capacitor filters, op-amps, and comparators. Such linear analog capacitors, therefore, require polysilicon layers which are highly doped as their electrodes. In addition, highly doped polysilicon layers are necessary to avoid the possible degradation of capacitor voltage coefficient due to the parasitic depletion of capacitance inside the polysilicon films. The voltage coefficient of the analog capacitors must be very low (on the order of 30 PPM/Volt) to reduce signal distortion to acceptable levels.
For these and other reasons, there is a need for an improved method of fabricating capacitors in an analog flash memory.
SUMMARY OF THE INVENTION
According to one embodiment of the present invention, a method of forming a capacitor on a substrate includes forming a first polysilicon layer overlying the substrate to define a floating gate. A second polysilicon overlying the first polysilicon layer is formed to define a control gate and a first electrode of the capacitor. A dielectric layer is formed over the second polysilicon layer. A third polysilicon layer is formed over the dielectric layer. The third polysilicon layer is etched to define a second electrode of the capacitor. Thereafter the dielectric layer is etched.


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