Capacitor electrodes arrangement with oxygen iridium between...

Details Capacitor electrodes arrangement with oxygen iridium between... Capacitor electrodes arrangement with oxygen iridium between...

2001-06-25

2003-06-03

Whitehead, Jr., Carl (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S306000, C257S753000, C257S763000

Reexamination Certificate

active

06573542

ABSTRACT:

BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to the area of semiconductor technology and concerns a microelectronic structure with a base substrate, a silicon-containing layer and an oxygen-barrier layer.
In order to achieve a further increase in the storage capacity of semiconductor memories, efforts are being made to use high-∈ dielectrics (∈>20) or ferroelectric dielectrics. During their deposition and conditioning, the preferred high-∈ and ferroelectric dielectric materials require temperatures of up to 800° C. and atmospheres containing oxygen. Under such conditions, however, prior art materials used for electrodes can be expected to undergo rapid oxidation. Therefore, the use of oxidation resistant electrode materials was also suggested. Platinum, for example, is a prominent example. When using platinum, however, the problem arises that direct contact of platinum with silicon at the high process temperatures leads to the interfering formation of platinum silicide. In addition, oxygen can diffuse through platinum relatively easily and oxidize the silicon located beneath it. For these reasons a barrier is necessary between the platinum electrode and a contact hole filled with polysilicon that connects the electrode with a selection transistor.
The barriers must meet, in particular, the following requirements. On the one hand they must prevent silicon from diffusing from the contact hole to the platinum electrode and, on the other, they must inhibit diffusion of oxygen from the platinum to the contact hole in order to exclude the electrically insulating oxidation of silicon. Moreover, the barriers themselves must be stable under the process conditions.
A possible design for a microelectronic structure as mentioned at the beginning—in the form of an electrode barrier system—is described, for example, in U.S. Pat. No. 5,581,439. There, a titanium nitride layer preventing the diffusion of silicon is buried in a silicon nitride layer, which protects the titanium nitride layer from oxidation, at least laterally. The silicon nitride collar supports a palladium base body with a platinum coating, which together form the electrodes. At the same time the titanium nitride layer should be protected from oxidation at least through the palladium.
In contrast, the design of a further electrode barrier system with other materials is described in the publication by J. Kudo et al., “A High Stability Electrode Technology for Stacked SrBi
2
Ta
2
O
9
Capacitors Applicable to Advanced Ferroelectric Memory”, IEDM 1997, pp. 609 to 612. In the design published there, a barrier of tantalum silicon nitride covered by a layer of pure iridium and a layer of iridium dioxide is preferred. The tantalum silicon nitride barrier prevents the diffusion of silicon but must itself be protected from oxidation. This task is performed by the iridium oxide layer and the pure iridium layer. It has been found, however, that at high temperatures, especially at 800° C., the pure iridium layer and the tantalum silicon nitride barrier together form iridium silicide, which has poor electrical conductivity.
The same problems also occur with the design favored by Saenger et al., “Buried, self-aligned barrier layer structures for perovskite-based memory devices including Pt or Ir bottom electrodes on silicon-contributing substrates”, J. Appl. Phys. 83(2), 1998, pp. 802-813. This publication reports that an interfering iridium silicide is formed from pure iridium and polysilicon during a recovery step in an atmosphere of nitrogen. This siliconization should therefore be prevented by a preceding recovery step in an atmosphere containing oxygen through complete oxidation of the iridium. Unfortunately this recovery step can be controlled only with difficulty, especially in respect of in-depth oxidation of the iridium, so that if the iridium layer is of uneven thickness oxidation of the polysilicon can also occur, resulting in an interruption of the electrical contact between the polysilicon and the iridium.
The use of a deposited pure iridium layer with subsequent oxygen treatment is also reported in the publication by Jeon et al., “Thermal stability of Ir/polycrystalline-Si structures for bottom electrode of integrated ferroelectric capacitors”, Appl. Phys. Lett. 71(4), 1997, pp. 467-469. On the other hand, the use of iridium dioxide as barrier is described in Cho et al., “Preparation and Characterization of Iridium Oxide Thin Films Grown by DC Reactive Sputtering”, Jpn. J. Appl. Phys. 36, 1997, pp. 1722-1727. Furthermore, the use of a multi-layer system of platinum, ruthenium and rhenium is known from Onishi et al., “A New High Temperature Electrode-Barrier Technology On High Density Ferroelectric Capacitor Structure”, IEDM 96, pp. 699-702; Bhatt et al., “Novel high temperature multilayer electrode-barrier structure for high-density ferroelectric memories”, Appl. Phys. Lett. 71(5), 1997, pp. 719-721; Onishi et al., “High Temperature Barrier Electrode Technology for High Density Ferroelectric Memories with Stacked Capacitor Structure”, Electrochem. Soc. 145, 1998, pp. 2563-2568; Aoyama et al., “Interfacial layers between Si and Ru Films Deposited by Sputtering in Ar/O2 Mixture Ambient”, Jpn. J. Appl. Phys. 37, 1998, pp. L242-L244.
A further barrier approach is proposed in U.S. Pat. No. 5,852,307, which describes the use of a slightly oxidized ruthenium layer and a ruthenium dioxide layer.
However, all of the barrier layers of prior art are accompanied by the risk that they are no longer sufficiently stable at the high process temperatures required, especially during a necessary temperature step for conditioning the high-∈ materials and/or the ferroelectric materials.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a microelectronic structure and a method for fabricating the structure which overcomes the above-mentioned disadvantageous of the prior art apparatus and methods of this general type, and in particular, to provide a microelectronic structure which is sufficiently stable at temperatures up to 800° C.
With the foregoing and other objects in view there is provided, in accordance with the invention a microelectronic structure, that includes: a base substrate; a silicon-containing layer; an oxygen-barrier layer; and an oxygen-containing iridium layer located between the silicon-containing layer and the oxygen-barrier layer. The oxygen-containing iridium layer is a sputtered layer that is fabricated by sputtering in an atmosphere containing oxygen at a temperature of at least 250° C. with a volume percent of oxygen in the atmosphere being between 2.5% and 15%.
The oxygen-containing iridium layer in the microelectronic structure prevents diffusion of silicon out of the silicon-containing layer and into the oxygen-barrier layer and any further layers arranged beyond it. To this end the oxygen-containing iridium layer contains a specific proportion of oxygen, which prevents the formation of iridium silicide and thereby the further diffusion of silicon. In addition, the boundary layer between the oxygen-containing iridium layer and the silicon-containing layer also remains essentially free of iridium silicide at temperatures up to at least 800° C. This can be proved, for example through resistance measurements of the oxygen-containing iridium layer. The absence of iridium silicide is indicated, for example, by a very low resistivity of the oxygen-containing iridium layer of less than 100 &mgr;ohm * cm, preferably even less than 30 &mgr;ohm * cm. In the presence of iridium silicide, which has a very high resistivity of approx. 6 ohm * cm, the resistivity of the structure formed from the silicon-containing layer and the oxygen-containing iridium layer would be considerably greater than 100 &mgr;ohm * cm. The low electrical resistance of the microelectronic structure is of considerable advantage, especially in maximally integrated semiconductor components—especially in semiconductor memories with structural sizes of 0.25 &mgr;m and below.
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