Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-10-31
1999-08-03
Booth, Richard A
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438749, 438756, H01L 218234
Patent
active
059337230
ABSTRACT:
A semiconductor processing method of forming a capacitor includes, a) providing a mass of electrically insulative oxide of a first density; b) densifying the oxide mass to a higher second density, the densified oxide mass being characterized by a wet etch rate of less than or equal to about 75 Angstroms/minute in a 100:1 by volume H.sub.2 O:HF solution; c) providing an electrically conductive inner capacitor plate over the underlying electrically insulative oxide layer and thereby defining an insulative layer and inner capacitor plate transition edge; d) after densifying the oxide mass, providing a capacitor dielectric layer over the inner capacitor plate and densified oxide mass, the capacitor dielectric layer comprising a nitride, the nitride containing capacitor dielectric layer having less thickness depletion at the transition edge than would otherwise occur were the oxide mass not subject to said densifying; and e) providing an electrically conductive outer capacitor plate over the capacitor dielectric layer. A capacitor construction includes, i) a dense mass of electrically insulative oxide; ii) an electrically conductive inner capacitor plate overlying and contacting the electrically insulative oxide mass; iii) a capacitor dielectric layer overlying the inner capacitor plate and oxide mass, the capacitor dielectric layer comprising a nitride; iv) an electrically conductive outer capacitor plate overlying the capacitor dielectric layer; and v) the dense mass of electrically insulative oxide contacting the inner capacitor plate being characterized by a wet etch rate of less than or equal to about 75 Angstroms/minute in a 100:1 by volume H.sub.2 O:HF solution.
REFERENCES:
patent: 4981810 (1991-01-01), Fazan et al.
patent: 5142438 (1992-08-01), Reinberg et al.
patent: 5145801 (1992-09-01), Chhabra
patent: 5155057 (1992-10-01), Dennison et al.
patent: 5286674 (1994-02-01), Roth et al.
patent: 5371026 (1994-12-01), Hayden et al.
patent: 5416041 (1995-05-01), Schwalke
patent: 5429979 (1995-07-01), Lee et al
patent: 5679595 (1997-10-01), Chen et al.
Kaga, T. et al., "A 0.29-vm.sup.2 MIM-Crown Cell And Process Technologies for Gigabit DRAMs", IEDM 1994, pp.927-929.
Carstensen Bob
Schuegraf Klaus Florian
Booth Richard A
Hack Jonathan
Micro)n Technology, Inc.
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