Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-07-22
2008-07-22
Booth, Richard A. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257SE21646
Reexamination Certificate
active
07402489
ABSTRACT:
A storage cell capacitor and a method for forming the storage cell capacitor having a storage node electrode including a barrier layer interposed between a conductive plug and an oxidation resistant layer. A layer of titanium silicide is fabricated to lie between the conductive plug and the oxidation resistant layer. An insulative layer protects the sidewalls of the barrier layer during the deposition and anneal of a dielectric layer having a high dielectric constant.
REFERENCES:
patent: 4623912 (1986-11-01), Chang et al.
patent: 4782309 (1988-11-01), Benjaminson
patent: 4903110 (1990-02-01), Aono
patent: 4910578 (1990-03-01), Okamoto
patent: 4982309 (1991-01-01), Shepherd
patent: 5005102 (1991-04-01), Larson
patent: 5046043 (1991-09-01), Miller et al.
patent: 5049975 (1991-09-01), Ajika et al.
patent: 5053351 (1991-10-01), Fazan et al.
patent: 5053917 (1991-10-01), Miyasaka et al.
patent: 5098860 (1992-03-01), Chakravorty et al.
patent: 5099305 (1992-03-01), Takenaka
patent: 5111355 (1992-05-01), Anand et al.
patent: 5134451 (1992-07-01), Katoh
patent: 5162248 (1992-11-01), Dennison et al.
patent: 5168073 (1992-12-01), Gonzalez et al.
patent: 5185689 (1993-02-01), Maniar
patent: 5187638 (1993-02-01), Sandhu et al.
patent: 5189503 (1993-02-01), Suguro et al.
patent: 5198384 (1993-03-01), Dennison
patent: 5227855 (1993-07-01), Momose
patent: 5248628 (1993-09-01), Okabe et al.
patent: 5293510 (1994-03-01), Takenaka
patent: 5335138 (1994-08-01), Sandhu et al.
patent: 5340765 (1994-08-01), Dennison et al.
patent: 5366920 (1994-11-01), Yamamichi et al.
patent: 5381302 (1995-01-01), Sandhu et al.
patent: 5387532 (1995-02-01), Hamamoto et al.
patent: 5391511 (1995-02-01), Doan et al.
patent: 5392189 (1995-02-01), Fazan et al.
patent: 5396094 (1995-03-01), Matsuo
patent: 5401680 (1995-03-01), Abt et al.
patent: 5471364 (1995-11-01), Summerfelt et al.
patent: 5489548 (1996-02-01), Nishioka et al.
patent: 5506166 (1996-04-01), Sandhu et al.
patent: 5631804 (1997-05-01), New
patent: 5796136 (1998-08-01), Shinkawata
patent: 5959327 (1999-09-01), Sandhu et al.
patent: 5973344 (1999-10-01), Ma et al.
patent: 6066528 (2000-05-01), Fazan et al.
patent: 6071770 (2000-06-01), Roh
patent: 6531730 (2003-03-01), Sandhu et al.
patent: 7015532 (2006-03-01), Sandhu et al.
patent: 0494313 (1992-07-01), None
Fujii, E. , et al., “ULSI DRAM technology with Ba/sub 0.7/Sr/sub 0.3/TiO/sub 3/ film of 1.3nm equivalent SiO/sub 2/ thickness and 10/sup -9/ A/cm/sup 2/ leakage current”,International Electron Devices Meeting 1992. Technical Digest,(1992),267-270.
Kaga, T , et al., “Crown-Shaped Stacked Capacitor Cell for 1.5-V Operation 64-Mb DRAMs”,IEEE Transactions on Electron Devices,38, (Feb. 1991),255-261.
Koyama, K. , et al., “A Stacked Capacitor with (Ba/sub x/Sr/sub 1-x/)TiO/sub 3/ for 256M DRAM”,Technical Digest, International Electron Devices Meeting,(Dec. 8-11, 1991),823-826.
Wolf, “Silicon Processing for the VLSI era”,Process Integration,vol. I,(1989),169-171.
“U.S. Appl. No. 08/314,117, Notice of allowance mailed Mar. 29, 1999”, 4 pgs.
“U.S. Appl. No. 08/572,392, Non Final Office Action mailed Apr. 8, 1999”, 10 pgs.
“U.S. Appl. No. 08/572,392, Notice of Allowance mailed Sep. 13, 1999”, 5 pgs.
“U.S. Appl. No. 08/572,392, Response filed Jul. 8, 1999 to Non Final Office Action mailed Apr. 8, 1999”, 3 pgs.
“U.S. Appl. No. 08/572,846, Advisory Action mailed Jul. 10, 1998”, 1 pg.
“U.S. Appl. No. 08/572,846, Final office action mailed May 1, 1998”, 7 pgs.
“U.S. Appl. No. 08/572,846, Non Final office action mailed Jun. 30, 1997”, 6 pgs.
“U.S. Appl. No. 08/572,846, Non Final office action mailed Oct. 8, 1998”, 4 pgs.
“U.S. Appl. No. 08/572,846, Notice of allowance mailed Feb. 22, 1999”, 2 pgs.
“U.S. Appl. No. 08/572,846, Response filed Jan. 8, 1999 to Non final office action mailed Oct. 8, 1998”, 4 pgs.
“U.S. Appl. No. 08/572,846, Response filed Jun. 24, 1998 to Final office action mailed May 1, 1998”, 5 pgs.
“U.S. Appl. No. 08/572,846, Response filed Dec. 17, 1997 to Non Final office action mailed Jun. 30, 1997”, 6 pgs.
“U.S. Appl. No. 09/362,326, Final office action mailed Jul. 20, 2001”, 7 pgs.
“U.S. Appl. No. 09/362,326, Non Final office action mailed Dec. 22, 2000”, 7 pgs.
“U.S. Appl. No. 09/362,326, Notice of allowance mailed May 7, 2002”, 4 pgs.
“U.S. Appl. No. 09/362,326, Notice of allowance mailed Sep. 24, 2002”, 5 pgs.
“U.S. Appl. No. 09/362,326, Response filed Apr. 23, 2001 to Non Final office action mailed Dec. 22, 2000”, 10 pgs.
“U.S. Appl. No. 09/362,326, Response filed Oct. 22, 2001 to Final office action mailed Jul. 20, 2001”, 3 pgs.
“U.S. Appl. No. 09/362,326, Advisory Action mailed Jan. 15, 2002”, 2 pgs.
“U.S. Appl. No. 09/362,326, Amendment under 37 CFR 1.116 filed Mar. 22, 2002”, 5 pgs.
“U.S. Appl. No. 09/362,326, Preliminary Amendment filed Jul. 27, 1999”, 2 pgs.
“U.S. Appl. No. 09/362,326, Preliminary Amendment filed Oct. 25, 1999”, 15 pgs.
Fazan Pierre C.
Sandhu Gurtej S.
Booth Richard A.
Micro)n Technology, Inc.
Schwegman Lundberg & Woessner, P.A.
LandOfFree
Capacitor compatible with high dielectric constant materials... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Capacitor compatible with high dielectric constant materials..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Capacitor compatible with high dielectric constant materials... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2816004