Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-08-21
2007-08-21
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C324S519000, C324S678000
Reexamination Certificate
active
11129656
ABSTRACT:
A method and apparatus for determining capacitance of wires in an integrated circuit is described. The capacitance information derived according to the invention can be used, for example, to calibrate a parasitic extraction engine or to calibrate an integrated circuit fabrication process. The capacitance information can also be used for timing and noise circuit simulations, particularly for deep sub-micron circuit design simulations. Briefly, the invention allows measurement of both total capacitance of a line and cross coupling capacitance between two lines by applying predetermined voltage signals to specific circuit elements. The resulting current allows simple computation of total capacitance and cross coupling capacitance. Multiple cross coupling capacitance can be measured with a single device, thus improving the art of library generation, and the overall method is free of uncertainties related to transistor capacitance couplings. The capacitance values obtained can then be used to calibrate procedures, processes, devices, etc.
REFERENCES:
patent: 5212454 (1993-05-01), Proebsting
patent: 5790436 (1998-08-01), Chen et al.
patent: 5901063 (1999-05-01), Chang et al.
patent: 5999010 (1999-12-01), Arora et al.
patent: 6011731 (2000-01-01), Beigel et al.
patent: 6249903 (2001-06-01), McSherry et al.
patent: 6300765 (2001-10-01), Chen
patent: 6366098 (2002-04-01), Froment
patent: 6414498 (2002-07-01), Chen
patent: 6934669 (2005-08-01), Suaya et al.
McGaughy et al., “A Simple Method for On-Chip, Sub-Femto Farad Interconnect Capacitance Measurement”, IEEE Electron Device Letters, vol. 18. No. 1, Jan. 1997.
Chen et al., Proper On-Chip Capacitance Measurement >> (1999). p. 1-5. Mentor Graphics www.mentor.com/dsm.
DeBroff et al., “Electromagnetic Concepts and Applications” (1996). p. 528-529, 534-535. Prentice-Hall Inc., ISBN 0-13-301151-8.
Chen et al., “An On-Chip, Attofarad Interconnect Charge-based Capacitance Measurement Technique”, IEEE, 1996, pp. 3.4.1-3.4.4.
Sylvester et al., “Investigation of Interconnect Capacitance Characterization using Charge-based Capacitance Measurement Technique and 3-D Simulation”, IEEE, 1997, pp. 491-494.
Gabillet Sophie H. M.
Suaya Roberto
Dinh Paul
Klarquist & Sparkman, LLP
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