Capacitance cell, semiconductor device, and capacitance cell...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S306000, C257S307000, C257S309000, C257SE29343

Reexamination Certificate

active

07872293

ABSTRACT:
A capacitance cell21is wired while using adjacent wiring layers Ma and Mb as a pair of electrode layers T1and T2orthogonally to opposed lateral end faces out of lateral end faces X1, X2, Y1, and Y2that section the cell in a plane direction. Contact surfaces of electrode surfaces T1and T2with the lateral end faces are second connection terminals T12and T22. For longitudinal pathways, first and second via contact layers V1and V2are connected. The first via contact layer V1interconnects the wiring layers Ma and Mb. The second via contact layer V2is connected to a wiring layer located outside beyond an upper or lower end face Z2, Z1. The second via contact layer V2is connected to a first connection terminal T11, T21located on the upper or lower end faces Z2, Z1. The capacitance cells21are linked via the first and second connection terminals so that a capacitance element having a free shape is formed. A capacitance cell, a semiconductor device, and a capacitance element arranging method that allow to arrange capacitance elements each using wiring layers sandwiching an interlayer insulating film with less of a leak current as electrode layers according to the shapes of unused areas.

REFERENCES:
patent: 7276776 (2007-10-01), Okuda et al.
patent: 2003/0161128 (2003-08-01), Masuda
patent: 2003/0206389 (2003-11-01), Hajimiri et al.
patent: 2005/0268445 (2005-12-01), Gallay et al.
patent: 2001-177056 (2001-06-01), None
patent: 2003-249559 (2003-09-01), None
patent: 2004-241762 (2004-08-01), None

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