Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
2001-02-28
2004-08-17
Butler, Dennis M. (Department: 2115)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C713S503000, C370S519000
Reexamination Certificate
active
06779123
ABSTRACT:
BACKGROUND
This invention relates to calibrating return time.
Digital electronics systems, such as computers, must move data among their component devices at increasing rates to take full advantage of the higher speeds at which these component devices operate. For example, a computer may include one or more processors that operate at frequencies of a gigahertz (GHz) or more. The data throughput of these processors outstrips the data delivery bandwidth of conventional systems by significant margins.
The digital bandwidth (BW) of a communication channel may be represented as:
BW=F
s
N
s
Here, F
s
is the frequency at which symbols are transmitted on a channel and N
s
is the number of bits transmitted per symbol per clock cycle (“symbol density”). Channel refers to a basic unit of communication, for example a board trace in single ended signaling or the two complementary traces in differential signaling.
Conventional strategies for improving BW have focused on increasing one or both of the parameters F
s
and N
s
. However, these parameters cannot be increased without limit. For example, a bus trace behaves like a transmission line for frequencies at which the signal wavelength becomes comparable to the bus dimensions. In this high frequency regime, the electrical properties of the bus must be carefully managed. This is particularly true in standard multi-drop bus systems, which include three or more devices that are electrically connected to each bus trace through parallel stubs.
Practical BW limits are also created by interactions between the BW parameters, particularly at high frequencies. For example, the greater self-induced noise associated with high frequency signaling limits the reliability with which signals can be resolved. This limits the opportunity for employing higher symbol densities.
Modulation techniques have been employed in some digital systems to encode multiple bits in each transmitted symbol, thereby increasing N
s
. Use of these techniques has been largely limited to point-to-point communication systems, particularly at high signaling frequencies. Because of their higher data densities, encoded symbols can be reliably resolved only in relatively low noise environments. Transmission line effects limit the use of modulation in high frequency communications, especially in multi-drop environments.
Information communicated over buses, like information communicated over other transmission lines, may experience delay with reference to a system clock or other timing mechanism.
REFERENCES:
patent: 6029250 (2000-02-01), Keeth
patent: 6581017 (2003-06-01), Zumkehr
patent: 6643787 (2003-11-01), Zerbe et al.
patent: 6665624 (2003-12-01), Simon et al.
Luca Satori and Bunnel G West, “The path to one-picosecond accuracy”, IEEE, ITC International Test Conference, pp. 619-627, Oct. 2000.
Amirtharajah Rajeevan
Simon Thomas D.
Butler Dennis M.
Fish & Richardson P.C.
Wang Albert
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