Calculating apparatus having a plurality of stages

Details Calculating apparatus having a plurality of stages Calculating apparatus having a plurality of stages

2006-03-21

2006-03-21

Huynh, Kim (Department: 2182)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C713S401000, C713S501000, C713S502000, C713S503000, C713S601000, C710S058000

Reexamination Certificate

active

07017064

ABSTRACT:
A calculating apparatus, or system, having a plurality of stages, such as in a pipeline arrangement, has the clocking rail or conductor positioned alongside the stages. With a large number, i.e., hundreds, of stages arranged in parallel sub-arrays, the clocking conductor is snaked alongside the sub-arrays. In individual stages it is arranged that the shortest of the two calculations taking place in a stage, takes place in the return path. An array can be divided into separate sections for independent processing.

REFERENCES:
patent: 4797848 (1989-01-01), Walby
patent: 4873456 (1989-10-01), Olisar et al.
patent: 4949249 (1990-08-01), Lefsky et al.
patent: 5001661 (1991-03-01), Corleto et al.
patent: 5101431 (1992-03-01), Even
patent: 5117490 (1992-05-01), Duxbury et al.
patent: 5210710 (1993-05-01), Omura
patent: 5313530 (1994-05-01), Iwamura
patent: 5321752 (1994-06-01), Iwamura et al.
patent: 5398262 (1995-03-01), Ahuja
patent: 5398284 (1995-03-01), Koopman, Jr. et al.
patent: 5414651 (1995-05-01), Kessels
patent: 5481573 (1996-01-01), Jacobowitz et al.
patent: 5499299 (1996-03-01), Takenaka et al.
patent: 5513133 (1996-04-01), Cressel et al.
patent: 5572690 (1996-11-01), Molnar et al.
patent: 5572714 (1996-11-01), Nakakura
patent: 5586307 (1996-12-01), Wong et al.
patent: 5600720 (1997-02-01), Iwamura et al.
patent: 5623683 (1997-04-01), Pandya
patent: 5666419 (1997-09-01), Yamamoto et al.
patent: 5724280 (1998-03-01), Davis
patent: 5742530 (1998-04-01), Gressel et al.
patent: 5764083 (1998-06-01), Nguyen et al.
patent: 5828870 (1998-10-01), Gunadisastra
patent: 5848159 (1998-12-01), Collins et al.
patent: 5859595 (1999-01-01), Yost
patent: 5867412 (1999-02-01), Suh
patent: 5867448 (1999-02-01), Mann
patent: 5907685 (1999-05-01), Douceur
patent: 5923871 (1999-07-01), Gorshtein et al.
patent: 5982900 (1999-11-01), Ebihara et al.
patent: 5987489 (1999-11-01), Monier
patent: 6005428 (1999-12-01), Amdahl
patent: 6026421 (2000-02-01), Sabin et al.
patent: 6069887 (2000-05-01), Geiger et al.
patent: 6088254 (2000-07-01), Kermani
patent: 6088453 (2000-07-01), Shimbo
patent: 6088800 (2000-07-01), Jones et al.
patent: 6122751 (2000-09-01), Janssens et al.
patent: 6144743 (2000-11-01), Yamada et al.
patent: 6151393 (2000-11-01), Jeong
patent: 6182233 (2001-01-01), Schuster et al.
patent: 6420663 (2002-07-01), Zelikson et al.
patent: 6618816 (2003-09-01), Ido et al.
patent: 6633995 (2003-10-01), Nam
patent: 3-17891 (1991-01-01), None
Blum, T., “Modular Exponentiation on Reconfigurable Hardware”, Thesis, Apr. 8, 1999, The Worcester Polytechnic Institute, Worcester.
Heshami, Nehrdad, et al., “A 250-MHZ Skewed-Clock Pipelined Data Buffer,”IEEE Journal of Solide-State Circuits, 31(3):376-383 (1996).

Affiliated with

Also associated with

Rating

Calculating apparatus having a plurality of stages does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Calculating apparatus having a plurality of stages, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Calculating apparatus having a plurality of stages will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3582700