Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1999-10-15
2001-09-11
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S118000
Reexamination Certificate
active
06289413
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to synchronous dynamic random access memory (SDRAM) device and, more particularly, to a cached SDRAM and a caching policy thereof.
2. Discussion of the Related Art
Turning now to
FIG. 1
, a block diagram of a standard SDRAM is shown, in particular, a 2Mbit×4 I/O×2 Bank SDRAM. Other configurations of SDRAMs are also known (e.g., 1Mbit×8 I/O×2 Bank, 512Mbit×16 I/O×2 Bank, etc.). The typical SDRAM
10
includes an address buffer
12
, first and second memory banks (
14
A,
14
B) and corresponding row decoders (
16
A,
16
B), column decoders (
18
A,
18
B), sense amplifiers (
20
A,
20
B), and data latches (
22
A,
22
B). Data input/output buffers
24
receive data to be written into a memory array (i.e., either array
14
A or
14
B) and output data read from a memory array (i.e., either array
14
A or
14
B).
An externally supplied system clock (CLK) signal is input to a clock buffer
26
(CLK Buffer), the CLK signal for providing system timing for the various function blocks of the SDRAM
10
. SDRAM
10
inputs are sampled on the rising edge of the CLK signal. An externally supplied clock enable signal (CKE) is input to a clock enable buffer
28
(CKE Buffer). The CKE buffer
28
provides an enable output to the CLK Buffer
26
and to a Self Refresh Clock
30
. CKE activates the CLK signal when in a high state and deactivates the CLK signal when low. By deactivating the clock CKE low initiates a Power Down mode, Suspend mode, or a Self Refresh mode. The Self Refresh Clock
30
and a Row Address Counter
32
operate in a standard manner for implementing the Self Refresh mode.
Address buffer
12
receives address inputs, A
0
-A
11
, and outputs information via address data lines
34
to the command decoder
36
, row decoders (
16
A,
16
B), column decoders (
18
A,
18
B), sequential controls (
38
A,
38
B) and mode register
40
. The data input/output buffer
24
provides input/outputs, corresponding to DQ
0
-DQ
3
.
The command decoder
36
outputs approximate command signals for executing a desired operation of the SDRAM
10
, in accordance with input signals which it receives. Examples of typical SDRAM operations include a Read operation and a Write operation. During a Read operation, upon the receipt of a Read command, the SDRAM
10
reads data from a particular memory location specified by the address received on the address lines. Similarly, during a Write operation, the SDRAM writes data received on the data input/output (I/O) lines DQ
0
-DQ
3
into a particular memory location specified by the address received on the address lines. In conjunction with the carrying out of SDRAM operations, the command decoder
36
receives buffered inputs including a chip select (CS), row address strobe {overscore (RAS)}, column address strobe {overscore (CAS)}, write enable WE, and a bank select (BS) input. In accordance with a first operation, the command decoder
36
provides a command signal to the row address counter
32
for performing a self refresh operation. In accordance with other operations, the command decoder
36
provides command signals to a mode register
40
, row/column select blocks (
16
A,
16
B) for each memory bank (
14
A,
14
B), and sequential control blocks (
38
A,
38
B) for each memory bank, as appropriate for carrying out the desired synchronous memory operation wherein the synchronous memory operation corresponds to a standard SDRAM command decoded by the command decoder on a rising or falling clock edge. The mode register
40
, for instance, provides a control signal to a respective sequential control (
38
A,
38
B) of each memory bank (
14
A,
14
B). The sequential control for each memory bank controls respective data latches associated with the respective memory bank. The Mode Register
40
receives input data via address buffer
12
for programming the operating mode, {overscore (CAS)}Latency, burst type (BT), and burst length as shown in FIG.
2
. The row/column select (
42
A,
42
B) for each memory bank (
14
A,
14
B) controls respective row decoders (
16
A,
16
B) and column decoders (
18
A,
18
B) associated with the respective memory bank (
14
A,
14
B). A buffered data mask input (DWM) is connected to the data input/output buffers
24
for selectively masking all or none of the data inputs or data outputs of the SDRAM chip
10
. Specific implementations for Read, Write, Refresh, and other typical operations of the SDRAM, as shown in
FIG. 1
, are known in the art and not further discussed herein.
As discussed above, synchronous DRAM products are generally known in the art. Industry standards for SDRAMs have been established, i.e., electrical and mechanical. Included in the standards for 16Mbit synchronous DRAM products, for example, is a requirement that all of the control, address and data input/output circuits are synchronized with the positive edge of an externally supplied clock. Additionally, prior to any access operation, the CAS latency, burst length, and burst sequence must be programmed into the device by address inputs A
0
-A
9
during a Mode Register Set cycle.
While standard synchronous DRAMS are designed to be flexible through programmability and to provide higher burst rates not achievable with asynchronous DRAMs, unfortunately, a standard SDRAM does not improve the initial latency of a page hit or miss. A page hit occurs during a read cycle when the row being accessed is already being sensed by the sense amplifiers and the memory array or bank is open. A page miss occurs during a read cycle when the row being accessed is not currently being sensed by the sense amplifiers, wherein the memory bank must first be closed, reactivated, refreshed, and reopened. Furthermore, the standard SDRAM does not reduce the penalties caused by the DRAM cycle time (t
RC
) and the DRAM precharge time (t
RP
). With multiple memory banks, a standard SDRAM does allow the user to perform simultaneous operations on both memory banks in order to hide some of the precharge and cycle time delays. However, this feature is only useful if the data being stored is orderly and can be organized such that the SDRAM can ping-pong between the two open banks uninterrupted. With today's multi-tasking computer operating systems, this is a formidable task. Standard SDRAMs thus suffer some performance limitations including, for instance, an inability to fully utilize the memory bandwidth and further having undesirable system wait states for all memory accesses.
SUMMARY OF THE INVENTION
An object of the present invention to solve performance issues of standard SDRAMs by reducing the latency of the memory and allowing simultaneous operations to occur on the same memory bank, that is, using a single memory bank of a multi-bank device.
Another object of the present invention is to enable a full utilization of memory bandwidth and to eliminate system wait states for all memory accesses.
According to the present invention, a cached synchronous dynamic random access memory (cached SDRAM) device having a multi-bank architecture and a programmable caching policy includes a synchronous dynamic random access memory (SDRAM) bank, the SDRAM bank including a row decoder coupled to a memory bank array for selecting a row of data in the memory bank array. Sense amplifiers are coupled to the memory bank array via bit lines for latching the row of data selected by the row decoder. A synchronous column selected means is provided for selecting a desired column of the row of data. A randomly addressable row register stores a row of data latched by the sense amplifiers. A select logic gating means is disposed between the sense amplifiers and the row register for selectively gating the row of data present on the bit lines to the row register in accordance to particular synchronous memory operations of the cached SDRAM being performed. Data to be input into cached SDRAM during a Write operation is received by the same amplifiers and written into the memory bank array. Data to
Bondurant David W.
Jones, Jr. Oscar Frederick
Mobley Kenneth J.
Rogers Jim L.
Tomashot Steven W.
Chace Christian P.
International Business Machines Corp.
Thai Tuan V.
Thornton Francis J.
Walsh Robert A.
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