Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2001-02-23
2004-02-10
Iqbal, Nadeem (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S042000, C714S710000, C714S718000
Reexamination Certificate
active
06691252
ABSTRACT:
RELATED APPLICATIONS
The present invention relates to commonly assigned, co-pending U.S. patent application Ser. No. 09/777,202, entitled “A SYSTEM FOR AND METHOD OF OPERATING A PROGRAMMABLE COLUMN FAIL COUNTER FOR REDUNDANCY ALLOCATION,” filed Feb. 2, 2001; and commonly assigned, concurrently filed U.S. patent application Ser. No. 09/792,320, entitled “SYSTEM AND METHOD OF OPERATING A PROGRAMMABLE COLUMN FAIL COUNTER FOR REDUNDANCY ALLOCATION,” the disclosures of which are hereby incorporated herein by reference.
TECHNICAL FIELD
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having spare memory cells for replacement of defective memory cells which are then programmably accessible.
BACKGROUND
Modern microprocessors and many Application Specific Integrated Circuits (ASICs) often incorporate large amounts of embedded memory. This memory is typically Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). These Random Access Memories (RAMs) constitute the majority of transistors contained on a chip and can occupy the largest portion of the surface area of a chip, i.e., chip “real estate.” Availability and usability of these RAMs becomes a priority to semiconductor manufacturers. Typically semiconductor manufacturers incorporate a test and a repair scheme which tests RAM cells within the chip and replaces defective RAM cells with spare cells included for that purpose. Typically, columns and/or rows of RAM cells are replaced rather than individual RAM cells. Row substitution may be performed by appropriate changes to the address decoder while column substitution may be performed by MUX selection of appropriate bit lines.
Traditionally, semiconductor manufacturers have used bit maps to determine which RAM columns and/or RAM rows need to be replaced with redundant RAM columns or RAM rows. Identification of defective memory cells is a particular problem when embedded on a microprocessor or ASIC device, since external or off-chip access for testing is limited by the number of pins available. Thus, semiconductor manufacturers have incorporated Built In Self Tests (BISTs) and Built In Self Repair (BISRs) to test and replace RAM cells. Special purpose built-in test hardware is described in detail in the commonly assigned and co-pending U.S. patent application Ser. No. 09/183,536, entitled, “A Flexible And Programmable BIST Engine for On-Chip Memory Array Testing and characterization,” filed Oct. 30, 1998, the disclosure of which is hereby incorporated herein by reference.
Typically RAM cells are tested for a number of faults which can be classified into two categories, simple faults and linked faults. Simple faults are those which occur independent of other faults but may induce failures in other cells. Linked faults are when two or more simple faults are acting on a single cell (i.e. multiple faults influencing each other). Simple faults can be further divided into Address Decoder Faults (ADFs) and Memory Cell Array Faults (MCAFs). ADFs are only present in the address decoder and result in the unavailability of a cell, the lack of an address to access a cell, an address accessing multiple cells, or a specific cell being accessible with multiple addresses.
MCAFs can be further broken down into single cell faults and faults which occur between memory cells. Single cell faults include Stuck At Faults (SAFs), Stuck Open Faults (SOFs), Transition Faults (TFs), and Data Retention Faults (DRFs). SAF means a specific cell is either “stuck” at zero or “stuck” at one regardless of the data attempted to be written into the cell. SOF indicates that a memory cell cannot be accessed because of an open line. A TF occurs when a memory cell cannot make a transition from zero to one, or from one to zero. And finally, a DRF occurs when a cell is unable to retain a particular logic value or state for a requisite period of time.
Coupling faults involve two cells. A first cell, the coupling cell, which is the source of the fault, and the second cell, the coupled cell, which is the cell that experiences the fault. These coupling faults can occur either when a transition occurs in the coupling cell or when a specific value is stored in the coupling cell. Transitions in a coupling cell can cause the coupled cell to change from a zero to a one, or vice versa, or can cause a zero or a one to be stored within the coupled cell. Additionally, certain values in coupling cells may bleed through to a coupled cell regardless of the value which should be stored in the coupled cell.
Tests which are applied in parallel to a plurality or group of memory cells, or march tests, consist of a sequence of elements, or “march elements,” in which a sequence of operations are defined and corresponding data signals are applied to various memory cells, typically one row or column at a time. The overall memory can be divided into memory groups and these tests can occur in parallel across memory groups. The address order determines the order in which the march test is applied to various address locations within a memory group. A march test may contain the following sequence: write zero, read zero, write one, read one, write zero, read zero. This march test would ensure that a zero could be stored in, and read from, a memory cell, that a one can be stored in, and read from, a memory cell, and that the memory cell can transition from a zero to a one, and from one to zero. These march tests are performed on the memory cells during BIST.
Once faulty memory cells have been identified, BISR is used to replace the faulty memory cells with spare memory cells. This typically occurs a column or row at a time or using multiple spare columns or rows to replace a continuous group of columns or rows (e.g., an address space spanning several rows or columns). Semiconductor manufacturers also combine BIST and BISR in accordance with their testing philosophy. BIST could be completed before the BISR has been implemented and not repeated after array reconfiguration in which faulty rows or columns are replaced with spare ones. Thus, if BIST is completed before BISR is performed, the replacement columns and rows are not typically tested during BIST and columns and rows of cells would be included in the operational memory array which have not successfully past BIST.
Alternatively, and more preferably, BIST and BISR can occur alternatively to ensure that each of the memory cells contained in the final (operational) memory array configuration have been thoroughly tested. For instance, one march test may occur during the first pass of BIST and be used to identify faulty memory cells. Once these faulty memory cells have been identified, a first pass of BISR can be used to replace the rows and/or columns of memory which contain these faulty memory cells. Once the first pass of BISR has been completed, the second pass of BIST can be performed which repeats the first BIST pass or which includes additional march tests to ensure that the replacement rows and/or columns, as configured, are operating properly. A second pass of BISR would be performed at the conclusion of the second pass of BIST to replace any newly identified or remaining faulty rows and/or columns. In addition, other march tests can be performed which test for coupling problems between memory cells in the reconfigured array. A BIST, which identifies memory cells with faults, is always followed by BISR, or the memory array is unrepairable and discarded.
Once a row of memory containing a non-operational cell has been identified, its address is typically stored and mapped to a redundant row. This mapping may occur after each row containing a non-operational cell has been identified, or alternatively, testing may be suspended while the row containing the non-operational cell is mapped to a redundant row. Once the mapping is completed, testing of the remaining rows is resumed. For memory addresses which cannot be accessed or stored in a single clock cycle a pipeline may be implemented to allow the access or storage t
Howlett Warren Kurt
Hughes Brian William
Damiano Anne L.
Hewlett--Packard Development Company, L.P.
Iqbal Nadeem
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