Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2007-09-25
2007-09-25
Bragdon, Reginald (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S118000
Reexamination Certificate
active
11019874
ABSTRACT:
We present, in an exemplary embodiment of the present invention, a novel method for providing cache refresh within a finite time window (i.e., a time-box) with predictable accuracy and given constrained resources. Instead of refreshing the entire cache in a specified time window, we introduce an error. As used herein, the term “error” refers to a period of time. By introducing error, we effectively and dynamically widen the time-box to distribute the refresh activity.
REFERENCES:
patent: 5761703 (1998-06-01), Bolyn
patent: 5901100 (1999-05-01), Taylor
patent: 6128701 (2000-10-01), Malcolm et al.
patent: 6570803 (2003-05-01), Kyung
patent: 6717863 (2004-04-01), Afghahi et al.
patent: 6760813 (2004-07-01), Wu
patent: 2004/0111413 (2004-06-01), Birbo et al.
patent: 200011687 (2000-01-01), None
English Abstract.
Chris Olston, et al., Adapative Precision Setting for Cached Approximate Values, ACM Sigmod 2 Santa Barbara, California, USA, pp. 355-366; May 2001.
Joe Chun-Hung Yuen, et al., Cache Invalidation Scheme for Mobile Computing Systems With Real-Record, vol. 29, No. 4, Dec. 2000, pp. 34-39.
Bragdon Reginald
F. Chau & Associates LLC
International Business Machines - Corporation
Willhite Tyler
LandOfFree
Cache refresh algorithm and method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Cache refresh algorithm and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cache refresh algorithm and method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3744648