Memory cell with trench-isolated transistor including first...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S513000, C257S647000, C257SE29020

Reexamination Certificate

active

11119128

ABSTRACT:
An isolation trench in a semiconductor includes a first isolation trench portion having a first depth and having a first sidewall intersecting a surface of the semiconductor at a first angle. A second isolation trench portion extends within and below the first isolation trench portion. The second isolation trench portion has a second depth and includes a second sidewall. The second sidewall intersects the first sidewall at an angle with respect to the surface that is greater than the first angle. A dielectric material fills the first and second isolation trench portions.

REFERENCES:
patent: 5536675 (1996-07-01), Bohr
patent: 5801083 (1998-09-01), Yu et al.
patent: 5874317 (1999-02-01), Stolmeijer
patent: 5915191 (1999-06-01), Jun
patent: 5969393 (1999-10-01), Noguchi
patent: 5994198 (1999-11-01), Hsu et al.
patent: 6034409 (2000-03-01), Sakai et al.
patent: 6081662 (2000-06-01), Murakami et al.
patent: 6087705 (2000-07-01), Gardner et al.
patent: 6154417 (2000-11-01), Kim
patent: 6171924 (2001-01-01), Wang et al.
patent: 6258688 (2001-07-01), Tsai
patent: 6274457 (2001-08-01), Sakai et al.
patent: 6342428 (2002-01-01), Zheng et al.
patent: 6350655 (2002-02-01), Mizuo
patent: 6355540 (2002-03-01), Wu
patent: 6380095 (2002-04-01), Liu et al.
patent: 6383931 (2002-05-01), Flanner et al.
patent: 01-282915 (1989-11-01), None
J. Chen et al.,Subbreakdown Drain Leakage Current in MOSFET,IEEE, pp. 515-517 (1987).
S. Lee et al.,Shallow Trench Isolation Characteristics with High-Density-Plasma Chemical Vapor Deposition Gap-Fill Oxide for Deep-Submicron CMOS Technologies,37 Jpn. J. Appl. Phys. 1222-1227 (1998).
M. Nandajumar et al.,Shallow Trench Isolation for Advanced ULSI CMOS Technologies,Silicon Technology Development, Kilby Center, Texas Instruments, 4 pages.(pre-Aug. 2000).
W. Tonti et al.,Impact of Shallow Trench Isolation on Reliabiltiy of Buried- and Surface-Chanel Sub-μm PFET,IEEE, pp. 24-29 (1995).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Memory cell with trench-isolated transistor including first... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory cell with trench-isolated transistor including first..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory cell with trench-isolated transistor including first... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3744649

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.