Cache memory utilizing pseudo static four transistor memory cell

Details Cache memory utilizing pseudo static four transistor memory cell Cache memory utilizing pseudo static four transistor memory cell

1994-06-01

1995-12-12

Nelms, David C.

Static information storage and retrieval

Systems using particular element

Flip-flop

365 49, 365203, 365222, G11C 1134, G11C 700

Patent

active

054756332

ABSTRACT:
A four transistor memory cell having a pair of cross coupled transistors and a pair of pass gates is disclosed. The four transistor memory cell is refreshed by charge transfer between the bit lines the internal nodes during bit line precharge.

REFERENCES:
patent: 5020028 (1991-05-01), Wanlass
patent: 5068825 (1991-11-01), Mahant-Shetti et al.
patent: 5111427 (1992-05-01), Kobayashi et al.
patent: 5325508 (1994-06-01), Parks et al.

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