Cache memory subsystem including a fixed latency R/W pipeline

Details Cache memory subsystem including a fixed latency R/W pipeline Cache memory subsystem including a fixed latency R/W pipeline

2007-07-31

2007-07-31

Elmore, Stephen C. (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S100000, C711S111000, C711S112000, C711S113000, C711S167000, C711S169000, C710S006000, C710S036000, C710S039000, C365S049130

Reexamination Certificate

active

10755734

ABSTRACT:
A cache memory subsystem including a fixed latency read/write pipeline. The cache memory subsystem includes a cache storage which may be configured to store a plurality of cache lines of data. The cache memory subsystem further includes a scheduler which may be configured to schedule reads and writes of information associated with the cache storage using a fixed latency pipeline. In response to scheduling a read request, the scheduler may be further configured to cause an associated write to occur a fixed number of cycles after the scheduling of the read request.

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