Cache memory flush scheme

Details Cache memory flush scheme Cache memory flush scheme

1982-09-08

1986-01-28

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365218, 365230, G11C 1140, G11C 700

Patent

active

045675783

ABSTRACT:
A method of setting a memory array to a common logic value by activating all the line switches by the precharge device for the duration of a word signal and simultaneously applying the common logic value directly to all the bit lines.

REFERENCES:
patent: 3845474 (1974-10-01), Lange et al.
patent: 3979726 (1976-09-01), Lanage et al.
patent: 3980899 (1976-09-01), Shimada et al.
patent: 4159540 (1979-06-01), Smith et al.
patent: 4172291 (1979-10-01), Owens et al.
patent: 4236207 (1980-11-01), Rado et al.
patent: 4247918 (1981-01-01), Iwahashi et al.
patent: 4360901 (1982-11-01), Proebsting
patent: 4439843 (1984-03-01), Takamatsu
patent: 4489404 (1984-12-01), Yasuoka
IBM Technical Disclosure Bulletin, vol. 20, No. 5 10/77.

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