Cache memory control system

Details Cache memory control system Cache memory control system

1979-03-22

1980-08-26

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365 49, G11C 1300

Patent

active

042198836

ABSTRACT:
Block information from a main memory, which is registered in an address register, is applied to a directory. A bank address in the main memory is taken out from the respective locations defined by the block information in each bank of the directory. A comparator compares the bank address with a bank address of the main memory registered in said address register. The output signal from the comparator is applied as a control signal to a control ROM. The directory memory applies an address signal to the control ROM. Upon the application of the address signal, the control ROM produces the contents (control information) of the location defined by the address signal and the contents is loaded into the directory memory. The control information determines the earliest used bank in the cache memory and determines the bank to which the contents of the main memory is loaded.

REFERENCES:
patent: 3821724 (1974-06-01), Warner
Japanese Patent Publication No. 43-4011 "Information Memory Device" published Feb. 14, 1968. _
Japanese Patent Publication No. 48-3445 "Memory System" published Jan. 31, 1973. _

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