Cache memory capable of selecting size thereof and processor...

Details Cache memory capable of selecting size thereof and processor... Cache memory capable of selecting size thereof and processor...

2005-10-11

2005-10-11

Lane, Jack A. (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S003000, C365S049130

Reexamination Certificate

active

06954827

ABSTRACT:
A multi-way set-associative cache memory is configured to operate only with those ways of the tag and data memories that operate normally, and excludes those ways of the tag and data memories that are determined to be incurably defective. By reducing the size of the cache memory to exclude the defective cells, the present invention is capable of preventing scrapping or discarding of the entire high-priced processor chip in which CPU and cache memory are integrated into a single chip.

REFERENCES:
patent: 5551004 (1996-08-01), McClure
patent: 6131143 (2000-10-01), Sakai
patent: 2003/0088811 (2003-05-01), Cherabuddi et al.
patent: 05-197622 (1993-08-01), None
patent: 10-254771 (1998-09-01), None

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