Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2006-01-10
2006-01-10
Anderson, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S170000
Reexamination Certificate
active
06986010
ABSTRACT:
A method and apparatus to speculatively allocate a combinable store request buffer for a cache lock operation by setting an extended lock indicator. The store request buffer is speculatively allocated and the load-lock micro-operation associated with the cache lock operation is sent to a replay loop. During the replay window, conflict detection processing is completed. When the load-lock micro-operation returns from replay, the store buffer is de-allocated if a conflict has been detected during the replay window.
REFERENCES:
patent: 5966544 (1999-10-01), Sager
patent: 5983329 (1999-11-01), Thaler et al.
patent: 6006299 (1999-12-01), Wang et al.
patent: 6163838 (2000-12-01), Merchant et al.
Cheong Hoichi
Lin Zhongru J.
Nye Jeffrey L.
Sutanto Edwin R.
Anderson Matthew
Bacon Shireen I.
Intel Corporation
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