Cache leakage shut-off mechanism

Details Cache leakage shut-off mechanism Cache leakage shut-off mechanism

2005-06-30

2010-02-02

Lee, Thomas (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S300000, C713S320000, C713S330000, C326S033000, C326S034000, C326S083000

Reexamination Certificate

active

07657767

ABSTRACT:
In one embodiment of the present invention, a technique is provided to control leakage of a cache sub-array. Other embodiments are disclosed herein. A sleep and shut-off circuit is connected between a virtual supply terminal and a first physical supply terminal to reduce leakage from the cache sub-array when the cache sub-array is disabled in a shut-off mode. The cache sub-array is connected between the virtual supply terminal and a second physical supply terminal. An active circuit is connected to the sleep and shut-off circuit in parallel to enable the cache sub-array in a normal mode and to disable the cache sub-array in the shut-off mode.

REFERENCES:
patent: 2753527 (1956-07-01), Adler
patent: 5781916 (1998-07-01), Hardage et al.
patent: 6977519 (2005-12-01), Bhavnagarwala et al.
patent: 2006/0119393 (2006-06-01), Hua et al.
patent: 2006/0206739 (2006-09-01), Kim et al.

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