Cache controller computer system and method for program...

Details Cache controller computer system and method for program... Cache controller computer system and method for program...

2006-07-18

2006-07-18

Nguyen, Hiep T. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C717S149000

Reexamination Certificate

active

07080204

ABSTRACT:
A computer system which dynamically extracts multiple threads from a program using a thread binary compiler (TBC), and a simultaneous multithreading (SMT) method. The computer system loads the TBC to a cache and controls the cache such that the TBC divides the program into multiple threads, and the cache loads the program as a recompiled program, whenever the cache loads a program stored in main memory.

REFERENCES:
patent: 6061710 (2000-05-01), Eickemeyer et al.
patent: 6289369 (2001-09-01), Sundaresan
patent: 6470443 (2002-10-01), Emer et al.
patent: 2002/0144060 (2002-10-01), Stoodley
patent: 05-324580 (1993-12-01), None
patent: WO 91/20033 (1991-12-01), None

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