Cache connection with bypassing feature

Details Cache connection with bypassing feature Cache connection with bypassing feature

2000-02-18

2004-04-27

Thai, Xuan M. (Department: 2187)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S310000, C710S100000, C710S029000, C710S033000, C711S117000, C711S119000, C711S120000, C711S138000, C709S213000

Reexamination Certificate

active

06728823

ABSTRACT:

TECHNICAL FIELD
The invention relates to computer memory systems. More particularly, the invention relates to multilevel cache memories.
BACKGROUND ART
In a computer system, the interface between a processor and memory is critically important to the performance of the system. Because fast memory is very expensive, memory in the amount needed to support a processor is generally much slower than the processor. In order to bridge the gap between fast processor cycle times and slow memory access times, cache memory is utilized. A cache is a small amount of very fast memory that is used to store a copy of frequently accessed data and instructions from main memory. A processor can operate out of this very fast memory and thereby reduce the number of wait states that must be interposed during memory accesses. When the processor requests data from memory and the data resides in the cache, then a cache read “hit” takes place, and the data from the memory access can be returned to the processor from the cache without incurring the latency penalty of accessing main memory. If the data is not in the cache, then a cache read “miss” takes place, and the memory request is forwarded to the main memory, as would normally be done if the cache did not exist. On a cache miss, the data that is retrieved from the main memory is provided to the processor and is also written into the cache due to the statistical likelihood that this data will be requested again by the processor in the near future.
The individual data elements stored in a cache memory are referred to as “lines.” Each line of a cache is meant to correspond to one addressable unit of data in the main memory. A cache line thus comprises data and is associated with a main memory address in some way. Schemes for associating a main memory address with a line of cache data include direct mapping, full association and set association, all of which are well known in the art.
A cache may be designed independently of the microprocessor, in which case the cache is placed on the local bus of the microprocessor and interfaced between the processor and the system bus during the design of the computer system. However, as the density of transistors on a processor chip has increased, processors may be designed with one or more internal caches in order to decrease further memory access times. An internal cache is generally small, an exemplary size being 256 Kb (262,144 bytes) in size. In computer systems that utilize processors with one or more internal caches, an external cache is often added to the system to further improve memory access time. The external cache is generally much larger than the internal cache(s), and, when used in conjunction with the internal cache(s), provides a greater overall hit rate than the internal cache(s) would provide alone.
In systems that incorporate multiple levels of caches, when the processor requests data from memory, the internal or first level cache is first checked to see if a copy of the data resides there. If so, then a first level cache hit occurs, and the first level cache provides the appropriate data to the processor. If a first level cache miss occurs, then the second level cache is then checked. If a second level cache hit occurs, then the data is provided from the second level cache to the processor. If a second level cache miss occurs, then the data is retrieved from main memory (or higher levels of caches, if present). Write operations are similar, with mixing and matching of the operations discussed above being possible.
In a multilevel cache system several forms of data transfer can take place. The possible data transfers include fills, loads, and stores. As used herein, a fill operation is the copying of a line from a higher level cache (further from a processor core) into a lower level cache (closer to a processor core); a load operation is the copying of at least a part of a line from a cache into the processor core—typically a register or general register file within the processor core; and a store operation is the moving of data from the processor core into a line of a cache. These data transfers are better understood by considering FIG.
1
.
FIG. 1
is a block diagram of a computer system
100
with two levels of caches. A processor core
105
is connected to an L0 cache
110
and an L1 cache
115
. The L1 cache
115
and the L0 cache
110
are solid state memory circuits. The L1 cache
115
, the L0 cache
110
and the processor core may be separate integrated circuits or physically packaged together in some combination (e.g., the L0 cache
110
and the processor core
105
together in the same integrated circuit package). The L0 cache
110
comprises a memory array
140
, which is a RAM (random access memory) where cache lines are stored.
Several buses connect among the processor core
105
, the L0 cache
110
and the L1 cache
115
. An L1 load bus
125
is a bus for loading data from the L1 cache
115
to the microprocessor core
105
. An L0 load bus
130
is a bus for loading data from the L0 cache
110
to the microprocessor core
105
. A store bus
135
supports storing operations from the microprocessor core
105
to the L0 cache
110
and/or the L1 cache
115
. Finally, a fill bus
120
supports transfers of lines from the L1 cache
115
to the L0 cache
110
. Because fills are larger than stores (or loads), fill data on the fill bus
120
is split into several sections, and each section is connected to a separate input port on the memory array
140
. The widths of the fill bus
120
is L bytes, while the width of the other buses is K bytes. As shown, L=4K with exemplary values being L=64 bytes and K=16 bytes.
SUMMARY OF THE INVENTION
In one respect, the invention is a method for using a data connection between a source and a cache. The cache comprises a memory array, and the cache is intermediate between the source and a target. The method comprises transferring data from the source to the cache along the data connection and transferring data from the source to the target along the data connection while bypassing the memory array. Preferably, the target is a processor core, and the cache is a level 0 cache with respect to the processor core. Alternatively, the target is a second cache. Preferably, the data connection is a bus, and in some cases the width of the data connection bus may be less than the width of a cache line in the memory array.
In another respect, the invention is an apparatus for conveying data from a source to at least one of a plurality of targets. The apparatus comprises a cache that is a first target, a second target, a first data connection and a second data connection. The cache comprises a memory array. The first data connection extends from the source to the cache, wherein data targeted at the cache is conveyed along the first data connection and wherein data targeted at the second target is conveyed along the first data connection while bypassing the memory array. The second data connection extends from the cache to the second target, wherein data targeted at the second target is conveyed along the second data connection. The source of the data targeted at the second target may be the cache or the source. Preferably, the second target is a processor core, and the cache is a level 0 cache with respect to the processor core. Alternatively, the second target is a second cache. Preferably, the first data connection and the second data connection are buses, and in some cases the width of the data connection buses may be less than the width of a cache line in the memory array.
In yet another respect, the invention is an apparatus. The apparatus comprises a memory array having an interface port, a first connection selectively coupled to the interface port, and a second connection selectively coupled to the interface port. Preferably, the first connection comprises a first tri-state buffer capable of driving signals from a first source to the interface port, and the second connection comprises a second tri-state buffer capable of driving signals fr

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