Cache coherency detection in a bus bridge verification system

Details Cache coherency detection in a bus bridge verification system Cache coherency detection in a bus bridge verification system

1997-07-31

1999-11-30

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711144, 711146, 370401, 370402, G06F 1208

Patent

active

059960507

ABSTRACT:
A methodology that provides detection of cache coherency errors in addition to detection of inefficient cache use by a cache master is disclosed. A model of the cache with storage for the address and data contained in each cache line and a flag indicating the state of the cache line (e.g., MESI state, or other cache coherency protocol state) is utilized. In addition, the cache model object also holds a dynamically allocated list (the cycle list) of bus cycles. This list is used to store pointers to non-cache bus cycles initiated in the multi-bus system. Cache bus cycles can update the state of the cache model object and can also instruct the cache model to perform coherency tests on pending non-cache bus cycles in the cycle list. When all protocol tests for a non-cache bus cycle have been successfully completed, no further coherency tests are performed on that bus cycle. Cache master verification is also achieved by polling the cache model to determine source of target resolution cycles for a bus cycle initiated by bus masters. Thus, cache coherency and cache controller operations are efficiently checked.

REFERENCES:
patent: 5440722 (1995-08-01), VanderSpek et al.
patent: 5499346 (1996-03-01), Amini et al.
patent: 5692202 (1997-11-01), Kardach et al.
patent: 5829032 (1998-10-01), Komuro et al.

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