Cache block store instruction operations where cache coherency i

Details Cache block store instruction operations where cache coherency i Cache block store instruction operations where cache coherency i

1997-03-17

1999-06-01

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711141, 711142, 711143, 711144, G06F 1212

Patent

active

059096985

ABSTRACT:
In a processor employing separate instruction and data caches in at least one cache hierarchy level, a cache control instruction forces modified data within the separate data cache to a lower cache hierarchy level. An existing cache access attribute is employed to distinguish between occasions when the data must be written all the way to main memory and occasions when the data need only be written to a cache hierarchy level from which fetches are made to the separate instruction cache. Thus, the separate instruction and data caches may be made coherent without writing all the way to main memory, but the ability to write modified data to main memory whenever necessary is preserved. Utilization of the existing attribute avoids increasing processor complexity and/or resources.

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Motorola Inc. and IBM Corp., "PowerPC 603: RISC Microprocessor User's Manual", MPC603UM/AD, pp. 5-23 and 5-28, 1994.

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