C4 joint reliability

Details C4 joint reliability C4 joint reliability

2009-01-09

2010-02-02

Nguyen, Thinh T (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257S738000, C257S739000, C257SE23021, C438S612000, C438S613000

Reexamination Certificate

active

07656035

ABSTRACT:
In one embodiment, the invention provides a method comprising fabricating a die bump on a die, the die bump being shaped and dimensioned to at least reduce the flow of solder material used, to attach the die bump to a package substrate, towards an under bump metallurgy (UBM) layer located below the die bump. Advantageously, the method may comprise performing a substrate reflow operation to attach the package substrate to the die bump, without performing a separate wafer reflow operation to reflow the die bump.

REFERENCES:
patent: 5793117 (1998-08-01), Shimada et al.
patent: 6053395 (2000-04-01), Sasaki
patent: 6586843 (2003-07-01), Sterrett et al.
patent: 6750549 (2004-06-01), Chandran et al.
patent: 6869750 (2005-03-01), Zhang et al.
patent: 2005/0067688 (2005-03-01), Humpston

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