Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Patent
1997-06-13
2000-09-26
Sheikh, Ayaz R.
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
710128, G06F 1300
Patent
active
061254193
ABSTRACT:
There are provided plural synchronous RAMs, a memory controller, a bus for inputting the signal output from the memory controller 1a to the synchronous RAMs, and a bus for inputting the signals output from the synchronous RAMs to the memory controller. Each of the buses has a main line and two stub lines connected to the trunk like. Each of the synchronous RAMs is connected to the corresponding stub line so that the sum of the bus length of the bus between the synchronous RAM and the memory controller and the bus length of the bus between the synchronous RAM and the memory controller is substantially constant among all of said synchronous RAMs. Therefore, the signal transmission time between the bus master and the plural bus slaves can be shortened without increasing the number of pins of the bus master while keeping the signal transmission time substantially constant among the plural bus slaves.
REFERENCES:
patent: 5548226 (1996-08-01), Takekuma et al.
patent: 5568063 (1996-10-01), Takekuma et al.
patent: 5663661 (1997-09-01), Dillon et al.
patent: 5668834 (1997-09-01), Takekuma et al.
"A Proposal for an Implementation of IEEE P1596.4 `Ramlink` Optimized for Small (Single-Board) Memory Systems", Hans Wiggers Memory Technology Center, Mar. 23, 1995, Hewlett Packard.
Osaka Hideki
Takekuma Toshitsugu
Umemura Masaya
Hitachi , Ltd.
Sheikh Ayaz R.
Wiley David A.
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