Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-09-17
2002-10-08
Hua, Ly V. (Department: 2131)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S043000
Reexamination Certificate
active
06463554
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to improvements in bus communications systems. More specifically, the invention relates to a method and apparatus for preventing errors from occurring in a computer system, by the addition to the system of a patcher which monitors the bus for the occurrence of a bus event which would potentially cause an error in the system, and which then interferes with the normal bus behavior, thereby preventing that event from occurring or being observed by other agents on the bus.
2. Background of the Prior Art
Computer systems or other logic systems may include components or combinations of elements which are subject to various failure mechanisms upon the occurrence of a particular set of conditions. Each such condition may be termed a “bug”. Each bug has a “bug signature”, which defines the set of circumstances which will cause the occurrence of the bug.
For example, a system component may fault when a first particular event is followed immediately by a second particular event, but will not fault if any other event occurs between the first and second. Or, a first component may change behavior or perhaps even crash when a second component issues a particular event when the first component is in a specific state. Such failure mechanisms are well known in the art.
In computer systems or other logic or communications systems, generally referred to as computer systems hereinafter, various of these bug signatures may center around events occurring on a bus which connects a plurality of agents. For example, a computer system may include a processor, a chipset, and other agents all coupled together by a system bus. It is well understood that there may exist bug signatures which involve particular communications between these agents over the bus.
Alternatively, bug signatures may exist within a more compact universe, in which a particular event or series of conditions wholly within a single chip or other agent may cause an internal or external error. These sorts of bugs may involve a plurality of functional units coupled together by an intra-chip bus, or they may even involve a sequence of states within a single unit.
Previously, logic analyzers and in-circuit emulators have been utilized to monitor computer bus traffic to determine the source and cause of an observed system error. Unfortunately, these tools only provide information which can be used to make a re-definition and re-manufacture (a new stepping) of the component having the bug, so that this new stepping of the component will not exhibit the bug. They cannot be used to prevent occurrence of the bug in existing components.
Also, it is well understood that particular kinds of “blocking bugs” may “hide” other bugs. The hidden bugs only occur, and can only be discovered for fixing, once the blocking bugs are fixed. Or, they may occur infrequently enough that they may be masked by other bugs.
If there are a series of these blocking bugs, the use of mere logic analyzers and in-circuit emulators may require a large number of steppings to achieve a functionally correct, bug-free component. This may cost a significant amount of time, money, and engineering effort. Finally, the logic analyzers and in-circuit emulators tend to be large and expensive, and are wholly inappropriate for use in fixing bugs in a large number of installed systems on an ongoing run-time basis.
It is, therefore, desirable to have an improved means for detecting the occurrence, or impending occurrence, of a bug, according to its bug signature, and for preventing the bug from occurring. It is desirable that this not require a stepping of the component. It is further desirable that this be inexpensive to implement in production quantity components. It is also desirable that it be programmable, so that it may be used to fix later-discovered bugs in an installed base of systems.
SUMMARY OF THE INVENTION
The present invention encompasses an apparatus which includes a bus, a first agent coupled to the bus, a second agent coupled to the bus for communicating to the first agent according to a bus protocol, and a patcher coupled to the bus for monitoring a communication from the second agent to the first agent to identify an event which would cause an error in the apparatus, and for modifying the communication such that the error is avoided. The invention also encompasses the method of operation of such an apparatus and of such a bus patcher.
The bus patcher includes a protocol watcher which is adapted for use with the bus, a state machine which is adapted to watch for the occurrence of known bug signatures on the bus, and a perturber which is adapted for intervening on the bus to prevent occurrence of the bugs which have those signatures. Any of the protocol watcher, state machine, and/or perturber may be programmable.
The bus patcher can be used during silicon debug to avoid blocking bugs and find bugs hiding behind them, to permit the blocking and hidden bugs to be fixed in fewer steppings of the silicon.
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Budelman Gerald A
Hobbs William A.
Kurts Tsvika
Oliver Kenneth B.
Peters Stephen J.
Blakely , Sokoloff, Taylor & Zafman LLP
Hua Ly V.
Intel Corporation
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