Bus interface circuit and receiver circuit

Details Bus interface circuit and receiver circuit Bus interface circuit and receiver circuit

2003-06-13

2004-02-03

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S227000, C365S203000, C365S208000, C365S207000, C326S027000, C326S026000

Reexamination Certificate

active

06687166

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a bus interface, and more particularly to a bus interface comprising an output circuit that drives a bus line, a precharge circuit that pre-charges the bus line, and a receiver circuit that receives a signal output to the bus line.
BACKGROUND OF THE INVENTION
A conventional bus control system for use in a memory device will be described.
FIG. 8
is a diagram schematically showing an example of a conventional system configuration of a memory device. Referring to
FIG. 8
, a plurality of memory cell sub-array blocks
200
l
-
200
m
are connected to a common bus line
210
to which a receiver circuit
220
is connected. The receiver circuit
220
receives data read from the sub-array blocks
200
l
-
200
m
and outputs the received data.
The sub-array blocks
200
l
-
200
m
each have the same configuration, with the configuration of the sub-array block
200
l
shown in the figure. The sub-array block
200
l
comprises a memory cell array
201
in which a plurality of word lines and bit lines, not shown, are arranged in row and column directions, respectively, with memory cells, each at the intersection of a bit line and a word line, arranged as an array; a word driver
202
for driving a word line selected by an X decoder, not shown, that receives an address signal; and a Y switch
203
for selecting a bit line selected by a Y decoder, not shown, that receives an address signal and connecting to a sense amplifier
204
. A pair of complementary bit lines (T, B: B is a complementary signal of a bit line T), which are selected by the Y switch
203
, are input to the sense amplifier
204
. When a sense enable signal SE is activated, the sense amplifier
204
performs sense operation and outputs a resultant signal SAT to an output circuit
205
. The output circuit
205
comprises an output buffer circuit composed of a PMOS transistor PM
201
and an NMOS transistor NM
201
connected in series between the high-potential power supply VDD and the low-potential power supply VSS; and a control circuit that controls the output buffer circuit. The output terminal of a NAND circuit
206
, which executes a NAND operation of the sense enable signal SE and the output signal SAT of the sense amplifier
204
, is connected to the gate of the PMOS transistor PM
201
. The output of a NOR circuit
207
, which executes a NOR operation of the inverted signal of the sense enable signal SE and the output signal SAT of the sense amplifier
204
, is connected to the gate of the NMOS transistor NM
201
.
The operation of the conventional output circuit
205
shown in
FIG. 8
will be outlined. When the sense enable signal SE is at a high level and the output signal SAT output from the sense amplifier
204
is at a high level, the output of the NAND circuit
206
falls to a low level, the PMOS transistor PM
201
is turned on, and the high-potential power upply VDD charges the bus line
210
to a high level.
When the sense enable signal SE is at a high level and the output signal SAT of the sense amplifier
204
is at a low level, the output of the NOR circuit
207
goes to a high level, the NMOS transistor NM
201
is turned on, and the electric charge on the bus line
210
is discharged to the low-potential power supply VSS and the bus line
210
is set to a low level.
FIG. 9
is a timing diagram showing an example of an operation of the conventional memory device shown in FIG.
8
. Referring to
FIG. 9
, SE indicates the sense enable signal, P indicates the voltage of the gate of the PMOS transistor PM
201
in
FIG. 8
(voltage of the node indicated by P in FIG.
8
), BS indicates the voltage waveform of the bus line
210
near (BS) the output circuit
205
in
FIG. 8
, BE indicates the voltage waveform of the bus line
210
near the input terminal of the receiver circuit
220
at the far-end (BE) of the output circuit
205
in
FIG. 8
, and OUT indicates the output signal waveform of the receiver circuit
220
.
The sense amplifier
204
is activated on a rising edge of the sense enable signal SE. When the output signal SAT of the sense amplifier
204
is at a high level, the output P of the NAND circuit
206
falls to a low level, the PMOS transistor PM
201
is turned on, and the bus line is charged by the high-potential power supply VDD. The voltage waveform of the bus line
210
at the input terminal of the receiver circuit
220
rises as BE in FIG.
9
. The receiver circuit
220
is a circuit that differentially receives the input terminal voltage and the reference voltage to perform differential amplification. When the voltage BE of the input terminal (a rise time thereof being slow) exceeds the reference voltage, the output signal OUT is switched from a high level to a low level. In this case, when the bus line
210
is long and its capacitive load becomes large, the rising slope of BE (slew rate) becomes more dull with an increase in delay time between the activation of the sense enable signal and the output of the output signal OUT. This delay time results in an increase in access time and becomes one of the limiting factors of the high-speed operation of the memory system.
On the other hand, an increase in current drive capability of the output buffer circuit in an attempt to speed up a transition time of a signal at the far-end of the bus line would lead to an increase in power consumption. An attempt to reduce the rise time of an output signal to the high-potential power supply in the output buffer circuit, requires that a ratio of gain factors &bgr; between the PMOS transistor and NMOS transistor, &bgr; p/ &bgr; n, be set to a large value and that the PMOS transistor size be large enough. Note that &bgr; is given as (&mgr;&egr;/t
oX
)(W/L), where, &mgr; is a carrier mobility, &egr; a dielectric constant of a gate insulating film, t
oX
is a thickness of the gate insulating film, W is a channel width, and L is a channel length.
SUMMARY OF THE DISCLOSURE
Accordingly, it is an object of the present invention to provide a bus system, a bus interface circuit, a receiver circuit, and a semiconductor device including the above mentioned circuits, which realize a high-speed operation with laying restraint on the increase of power consumption or without increasing power consumption.
The above and other objects are attained by a bus interface circuit according to one aspect of the present invention, which comprises a precharge circuit including a switch element that is inserted between a bus line and a precharge power supply terminal and that is turned on or off based on a precharge control signal controlling a precharge operation, the precharge circuit precharging the bus line to a predetermined precharge voltage via the switch element that is turned on by the precharge power supply terminal during the precharge operation, wherein the precharge voltage is a predetermined voltage between two power supply voltages of two power supplies, first and second, which drive a receiver circuit and/or an output circuit, the receiver circuit receiving a signal output from the output circuit to the bus line and wherein the output circuit comprises means for outputting an output signal to the bus line, a logic amplitude of the output signal being determined by the precharge voltage and a predetermined fixed voltage which is one of the first and second power supply voltages.
In the bus interface circuit according to the present invention, the output circuit preferably comprises means that drives the bus line, which is precharged to the precharge voltage, to set the voltage of the bus line from the precharge voltage to the predetermined fixed voltage when a signal to be output to the bus line is at a first logic level corresponding to the first power supply and that does not drive the bus line but holds the voltage of the bus line at the precharge voltage when a signal to be output to the bus line is at a second logic level corresponding to the second power supply.
According to the present invention, the bus line is precharged to the precharge voltage, and the output

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