Bus having a dynamic timing bridge

Details Bus having a dynamic timing bridge Bus having a dynamic timing bridge

2006-07-31

2010-06-29

Lee, Thomas (Department: 2116)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S401000, C713S503000, C327S161000, C375S355000, C710S110000, C710S317000

Reexamination Certificate

active

07747889

ABSTRACT:
A data processing system may comprise an initiator device having an output whose timing is referenced by a clock input alone corresponding to a first delay along a signaling path. The exemplary data processing system further may further comprise a target device having an input whose timing is referenced by a clock input alone corresponding to a second delay along the signaling path and a system bus interconnected between the initiator device and the target device within the signaling path. The exemplary data processing system may further comprise a dynamic timing bridge coupled to the system bus within the signaling path, wherein responsive to a control signal representative of at least one system characteristic, the dynamic timing bridge performs one selected from the group consisting of (i) inserting a cyclic latency within the signaling path and (ii) not inserting the cyclic latency within the signaling path.

REFERENCES:
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patent: 7373450 (2008-05-01), Kamegawa
patent: 2004/0059446 (2004-03-01), Goldberg et al.

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