Bus controller

Details Bus controller Bus controller

2007-06-12

2007-06-12

Dang, Khanh (Department: 2111)

Electrical computers and digital data processing systems: input/

Access arbitrating

Centralized arbitrating

C710S113000

Reexamination Certificate

active

10802933

ABSTRACT:
A bus controller is provided including a processing means for performing processings of levels having cycle numbers which are different dependent on requesters which respectively issue an access request to a common memory. When it is expected from the present cycle number that a limit cycle number is exceeded, the bus controller selects a processing level with which the processing is performed with a smaller cycle number, or performs a control of giving no permission to a non-realtime bus access request. Thereby, it is possible to design a system with a cycle number that is smaller than the total sum of the maximum access cycle numbers multiplied by the maximum access times over all requesters.

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