Bus bridge with distribution of a common cycle clock to all brid

Details Bus bridge with distribution of a common cycle clock to all brid Bus bridge with distribution of a common cycle clock to all brid

1997-12-30

2000-02-29

Thai, Xuan M.

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

710129, 710131, 713600, G06F 1342, H04L 700

Patent

active

060322616

ABSTRACT:
A bus bridge for interconnecting a plurality of buses, which bridge includes a plurality of bridge portals, each portal being coupled to a respective one of the buses, and further includes a plurality of switching subsystems, each of which is coupled to a respective one of the bridge portals. The plurality of switching subsystems collectively constitute a switching system which interconnects the plurality of bridge portals. The bus bridge further includes a plurality of cycle clock subsystems, each of which is operatively associated with a respective bridge portal and the respective switching subsystem coupled thereto. Each cycle clock subsystem includes a cycle clock generator which generates a cycle clock, and a cycle counter which receives the cycle clock at a reset input thereof and produces a cycle count output which constitutes a common timing reference for the respective switching subsystem and the respective bridge portal. The bus bridge is preferably an IEEE 1394 serial bus bridge. Various specific implementations of the switching subsystems and bridge portals are disclosed.

REFERENCES:
patent: 5799207 (1998-08-01), Wang et al.
patent: 5831805 (1998-11-01), Sekine et al.
patent: 5838876 (1998-11-01), Iwamura
patent: 5848367 (1998-12-01), Lotockey et al.
patent: 5883621 (1999-03-01), Iwamura
patent: 5909559 (1999-06-01), So

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