Bus architecture techniques employing busses with different...

Details Bus architecture techniques employing busses with different... Bus architecture techniques employing busses with different...

2006-10-31

2006-10-31

Perveen, Rehana (Department: 2112)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C711S141000, C710S311000

Reexamination Certificate

active

07130953

ABSTRACT:
An integrated circuit system (70) includes a processor (130) and a system bus (12) with a first complexity coupled to the processor. Apparatus for enabling communication between the processor and one or more devices through the system bus include a first device (90), a second device (80), and a first bus interface (72) coupled to the system bus (12), coupled to the first device (90) through a first bus (92) with a second complexity less than the first complexity and coupled to the second device (80) through a second bus (82) with a third complexity less than the first complexity.

REFERENCES:
patent: 5727172 (1998-03-01), Eifert et al.
patent: 5812800 (1998-09-01), Gulick et al.
patent: 5828852 (1998-10-01), Niedermeier et al.
patent: 6112311 (2000-08-01), Beardsley et al.
patent: 6298420 (2001-10-01), Chittor et al.
patent: 6363448 (2002-03-01), Waller et al.
patent: 6532511 (2003-03-01), Brooks
patent: 6598110 (2003-07-01), Nally et al.
patent: 6636947 (2003-10-01), Neal et al.
patent: 2003/0212823 (2003-11-01), Anderson et al.
MIPS, “MIPS SOC-it™ 101 System Controller Family Datasheet” Online! Nov. 30, 2002, MIPS Technologies Inc. , Internet, XP002288979 Retrieved from the Internet: URL:http://www.mips.com/content/Documentation/MIPSDocumentation/SystemControllerIP/MD00164-2B-SOCIT101-DTS-01.01.pdf> ′retrieved on Jul. 19, 2004!.
MIPS: “SOC-it Press Presentation” ′Online! Jul. 29, 2002, MIPS Technologies Inc., Internet, XP002288980 Retrieved from the Internet URL:http//www.mips.com/content/PressRoom/PressKits/files/SOC-it—Press—Presentation.pdf> ′retrieved on Jul. 19, 2004!.
Aldworth P J: “System-on-a-chip bus architecture for embedded applications” Computer Design, 1999. (ICCD '99). International Conference on Austin, TX, USA Oct. 10-13, 1999, Los Alamitos, CA, USA, IEEE Comput. SOC, US, Oct. 10, 1999, pp. 297-298, XP010360495 ISBN: 0-76950-0406-X.
IBM: “The CoreConnect Bus Architecture” IBM, 1999, XP002204519.
Arm: “AMBA Specification (Rev. 2.0)” May 13, 1999, Arm XP002288981.
Flynn D: “AMBA: Enabling Reusable On-Chip Designs” IEEE Micro, IEEE Inc. New York, US, vol. 17, No. 4, Jul. 1, 1997, pp. 20-27, XP000658531.

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